https://github.com/pvgupta24/von-neumann-architecture-cpu

Implementation of 8-Bit CPU based on Von-Neumann Architechture in HDL
https://github.com/pvgupta24/von-neumann-architecture-cpu

cpu cpu-simulator verilog verilog-hdl von-neumann

Last synced: 3 months ago
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Implementation of 8-Bit CPU based on Von-Neumann Architechture in HDL

• Host: GitHub
• URL: https://github.com/pvgupta24/von-neumann-architecture-cpu
• Owner: pvgupta24
• Created: 2017-10-30T14:11:28.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2017-11-16T10:10:17.000Z (over 8 years ago)
• Last Synced: 2025-10-30T16:19:33.118Z (7 months ago)
• Topics: cpu, cpu-simulator, verilog, verilog-hdl, von-neumann
• Language: Verilog
• Homepage:
• Size: 204 KB
• Stars: 6
• Watchers: 1
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
## 8-Bit Von Neumann Architecture CPU

#### Contributors 

- Praveen Kumar Gupta

- Durvesh Bhalekar

### Abstract

> This verilog program shows the simulation of a 8-bit processor built on the principles of the Von Neumman architecture.

> The program can be loaded in the RAM module and the following code carries out the instructions accordingly. 

### Functionalities   

> This processor allows supported instructions (as given in the Instruction Set file) to be written in the RAM module.

![Instruction Set](Instruc_Set.png)

> An Instruction cycle is broken into 3 phases - Fetch , Decode and Execute

> Instructions from RAM Module are fetched into the Instruction Register on the appropriate phase, it is decoded by the control unit which sets various flags and select lines depending on the type of instruction, like 

> * fetching into immediate register

> * writing in register file

> * changing PC value

> * selecting address from imm. or PC

> * selecting the correct register from RF

> * Deciding the ALU operation

> * Sending the ALU output to the required place.

## Software Requirements

- Logisim

- iverilog

- gtkwave

## Usage Instructions

* Open either Behavioural or Dataflow Modelling Verilog file for CPU.

* From the given Instruction Set table, write 8-Bit binary instructions

  in the given RAM module at the end of the file.

* Sample instructions are already present. Overwrite it if needed.

* Enable Simulation.

  Compile the file as

        ` iverilog VerilogBM-210-235.v Verilog-210-235.v -o Verilog-210-235.vvp `

  Run the vvp file as

  

        ` vvp Verilog-210-235.vvp ` 

  Open the output wave as

  

        ` gtkwave VerilogBM-210-235.vcd `

Corresponding changes can be seen in the wave as per instructions.

## References

- Computer Organization and Design - Book by David Patterson and John Hennessy

- [Computer Architechture Tutorials](http://minnie.tuhs.org/CompArch/Tutes/week03.html)