https://github.com/quartiq/urukul
CPLD gateware for the Sinara Urukul module
https://github.com/quartiq/urukul
artiq cpld fpga migen sinara-hw
Last synced: 15 days ago
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CPLD gateware for the Sinara Urukul module
- Host: GitHub
- URL: https://github.com/quartiq/urukul
- Owner: quartiq
- License: gpl-3.0
- Created: 2017-09-03T18:32:54.000Z (over 7 years ago)
- Default Branch: master
- Last Pushed: 2021-11-18T23:51:16.000Z (over 3 years ago)
- Last Synced: 2025-05-08T22:44:43.887Z (15 days ago)
- Topics: artiq, cpld, fpga, migen, sinara-hw
- Language: Python
- Homepage: https://github.com/sinara-hw/Urukul/wiki
- Size: 59.6 KB
- Stars: 2
- Watchers: 5
- Forks: 12
- Open Issues: 4
-
Metadata Files:
- Readme: README.md
- License: LICENSE.GPL-3
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README
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# Urukul CPLD code
[Urukul overview](https://github.com/sinara-hw/Urukul/wiki)
[Urukul Schematics/Layout](https://github.com/sinara-hw/Urukul/releases)
[NU-Servo](https://github.com/m-labs/nu-servo)
## Building
Needs [migen](https://github.com/m-labs/migen) and [Xilinx ISE](https://www.xilinx.com/products/design-tools/ise-design-suite.html). Assumes ISE is installed in ``/opt/Xilinx``.
```
make
```
## Flashing
With Digilent [JTAG HS2](https://store.digilentinc.com/jtag-hs2-programming-cable/) cable:
- download firmware to dongle. Manually (adjust USB bus as needed):
```
/sbin/fxload -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D /dev/bus/usb/001/*`cat /sys/bus/usb/devices/1-3/devnum`
```
or automatically via the ``udev`` rule:
```
SUBSYSTEM=="usb", ACTION="add", ATTR{idVendor}=="0403", ATTR{idProduct}=="6014", ATTR{manufacturer}=="Digilent", RUN+="/usr/bin/fxload -v -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D $tempnode"
```
- install [xc3sprog](http://xc3sprog.sourceforge.net/)
- ``flash_xc3.sh jtaghs2``
- look for ``Verify: Success``
# License
GPLv3+