https://github.com/racerxdl/riskow

Learning how to make a RISC-V
https://github.com/racerxdl/riskow

fpga learning-exercise open-core opencore risc-v riskow verilog

Last synced: about 1 month ago
JSON representation

Learning how to make a RISC-V

• Host: GitHub
• URL: https://github.com/racerxdl/riskow
• Owner: racerxdl
• License: apache-2.0
• Created: 2020-12-18T01:53:38.000Z (about 4 years ago)
• Default Branch: main
• Last Pushed: 2021-05-09T06:14:46.000Z (over 3 years ago)
• Last Synced: 2024-11-07T00:50:01.798Z (3 months ago)
• Topics: fpga, learning-exercise, open-core, opencore, risc-v, riskow, verilog
• Language: Verilog
• Homepage:
• Size: 186 KB
• Stars: 131
• Watchers: 7
• Forks: 9
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

        

```

 mmmmm  mmmmm   mmmm  m    m  mmmm m     m

 #   "#   #    #"   " #  m"  m"  "m#  #  #

 #mmmm"   #    "#mmm  #m#    #    #" #"# #

 #   "m   #        "# #  #m  #    # ## ##"

 #    " mm#mm  "mmm#" #   "m  #mm#  #   #

                 (__)

                 (oo)

           /------\/

          / |    ||

         *  /\---/\

            ~~   ~~

..."Have you mooed today?"...

```

RISC-V Processor made in livestream at twitch: https://www.youtube.com/playlist?list=PLEP_M2UAh9q52a-w3ZUEChEoG_ROeMa88 (PT-BR)