https://github.com/rafaelcalcada/rvx

RISC-V microcontroller IP core developed in Verilog
https://github.com/rafaelcalcada/rvx

core cpu gpio mcu microcontroller processor risc-v riscv rv32i rvx spi system-on-chip uart zicsr

Last synced: 1 day ago
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RISC-V microcontroller IP core developed in Verilog

• Host: GitHub
• URL: https://github.com/rafaelcalcada/rvx
• Owner: rafaelcalcada
• License: mit
• Created: 2020-05-03T19:29:10.000Z (almost 5 years ago)
• Default Branch: main
• Last Pushed: 2025-04-13T13:59:04.000Z (10 days ago)
• Last Synced: 2025-04-13T14:35:24.533Z (10 days ago)
• Topics: core, cpu, gpio, mcu, microcontroller, processor, risc-v, riscv, rv32i, rvx, spi, system-on-chip, uart, zicsr
• Language: Verilog
• Homepage: https://rafaelcalcada.github.io/rvx/
• Size: 190 MB
• Stars: 172
• Watchers: 11
• Forks: 22
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • Contributing: CONTRIBUTING.md
  • License: LICENSE
  • Authors: AUTHORS.md

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README

        
RISC-V Steel


RISC-V Steel is a microcontroller design developed in Verilog that implements the RV32I instruction set of RISC-V. It is designed for easy, seamless integration into embedded systems, systems-on-chip (SoC), and FPGA designs, facilitating the rapid development of innovative RISC-V applications.

RISC-V Steel can run real-time operating systems such as FreeRTOS, as well as bare-metal embedded software. Its design includes components such as memory, timers, and interfaces for UART, GPIO, and SPI communication, enabling RISC-V Steel to integrate with a variety of sensors and actuators commonly used in embedded applications.

Check out [RISC-V Steel Documentation][1].

## Get Started

The quickest way to get started is to implement one of the example projects on your FPGA. Check it out:

- [Hello World Example][2]

- [FreeRTOS Example][3]

See the [User Guide][4] to learn how to create your own applications.

## License

RISC-V Steel is distributed under the [MIT License][5].

## Need help?

Please open a [new issue][6].

[1]: https://riscv-steel.github.io/riscv-steel

[2]: https://riscv-steel.github.io/riscv-steel/examples/helloworld

[3]: https://riscv-steel.github.io/riscv-steel/examples/freertos

[4]: https://riscv-steel.github.io/riscv-steel/userguide/

[5]: LICENSE

[6]: https://github.com/riscv-steel/riscv-steel/issues