https://github.com/raleighlittles/basys3countdownclock

Extremely basic countdown clock project for the Basys 3 FPGA development board.
https://github.com/raleighlittles/basys3countdownclock

basys-3 basys3 fpga hdl seven-segment-display verilog vivado xdc xilinx

Last synced: 6 days ago
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Extremely basic countdown clock project for the Basys 3 FPGA development board.

• Host: GitHub
• URL: https://github.com/raleighlittles/basys3countdownclock
• Owner: raleighlittles
• Created: 2019-02-18T05:41:40.000Z (almost 6 years ago)
• Default Branch: master
• Last Pushed: 2019-02-18T05:53:00.000Z (almost 6 years ago)
• Last Synced: 2024-11-28T03:12:29.914Z (2 months ago)
• Topics: basys-3, basys3, fpga, hdl, seven-segment-display, verilog, vivado, xdc, xilinx
• Language: Verilog
• Size: 5.86 KB
• Stars: 3
• Watchers: 2
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# About

*Very* basic implementation of a countdown clock, written for the [Basys 3 FPGA trainer board](https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/).

Uses the 4 7-segment displays available to start counting down from 9999 to 0 and then back to 9999 again.

# Setup

## Pre-requisites

* [Vivado Design Suite](https://www.xilinx.com/products/design-tools/vivado.html) 

## Instructions

* Import source and constraints file

* Run Synthesis

* Run Implementation

* Generate bitstream