https://github.com/rauhul/ece385

Digital Systems Laboratory UIUC FA 2016
https://github.com/rauhul/ece385

altera fpga quartus-prime systemverilog verilog

Last synced: about 2 months ago
JSON representation

Digital Systems Laboratory UIUC FA 2016

• Host: GitHub
• URL: https://github.com/rauhul/ece385
• Owner: rauhul
• Created: 2017-02-24T02:28:45.000Z (almost 8 years ago)
• Default Branch: master
• Last Pushed: 2017-02-24T02:35:52.000Z (almost 8 years ago)
• Last Synced: 2024-10-15T22:24:48.756Z (3 months ago)
• Topics: altera, fpga, quartus-prime, systemverilog, verilog
• Language: Verilog
• Homepage:
• Size: 55.5 MB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0

Awesome Lists containing this project