https://github.com/rauhul/ece385

Digital Systems Laboratory UIUC FA 2016
https://github.com/rauhul/ece385

altera fpga quartus-prime systemverilog verilog

Last synced: 2 days ago
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Digital Systems Laboratory UIUC FA 2016

• Host: GitHub
• URL: https://github.com/rauhul/ece385
• Owner: rauhul
• Created: 2017-02-24T02:28:45.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2017-02-24T02:35:52.000Z (over 8 years ago)
• Last Synced: 2025-08-03T10:38:29.471Z (2 months ago)
• Topics: altera, fpga, quartus-prime, systemverilog, verilog
• Language: Verilog
• Homepage:
• Size: 55.5 MB
• Stars: 2
• Watchers: 0
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
# ece385

Digital Systems Laboratory UIUC FA 2017