https://github.com/rejunity/atari-2600-fpga

Continue development of Atari 2600 in Verilog. Based on the original work by Daniel Beer.
https://github.com/rejunity/atari-2600-fpga

atari-2600 atari2600 fpga retrogaming verilog

Last synced: 8 days ago
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Continue development of Atari 2600 in Verilog. Based on the original work by Daniel Beer.

• Host: GitHub
• URL: https://github.com/rejunity/atari-2600-fpga
• Owner: rejunity
• Created: 2021-11-26T15:35:32.000Z (about 3 years ago)
• Default Branch: main
• Last Pushed: 2021-11-28T11:30:27.000Z (about 3 years ago)
• Last Synced: 2025-01-19T21:48:51.873Z (13 days ago)
• Topics: atari-2600, atari2600, fpga, retrogaming, verilog
• Language: Verilog
• Homepage:
• Size: 107 KB
• Stars: 0
• Watchers: 3
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Atari-2600

Atari 2600 in Verilog.

Based on the Daniel Beer's earlier work ["Atari on an FPGA"](https://people.ece.cornell.edu/land/courses/eceprojectsland/STUDENTPROJ/2006to2007/dbb26/dbb28_meng_report.pdf).

## Plan

1. Replace CPU 6502 VHDL implementation with Verilog.

    - [ ] Integrate Andrew Holme [Verilog 6502](http://www.aholme.co.uk/6502/Main.htm) core

    - [ ] Integrate Arlet Ottens [Verilog 6502](https://github.com/Arlet/verilog-6502) core

- Minimize vendor dependent code, move it out of the main files.

    - [ ] Remove PLL from mySystem.v

    - [ ] Separate folder for IceBreaker and Altera specific code

- Make codebase compatible with the open-source tools: [iverilog](http://iverilog.icarus.com/), [yosys](https://github.com/YosysHQ/yosys).

    - [ ] Makefile

- Testbench, coco_tb, compare to python emu

- Try to fit on open-source [iCEBreaker FPGA](https://www.crowdsupply.com/1bitsquared/icebreaker-fpga) (Lattice iCE40UP5k).

- [ASIC](https://www.zerotoasiccourse.com/)! :)