https://github.com/rggen/rggen-sample-testbench
https://github.com/rggen/rggen-sample-testbench
systemverilog uvm uvm-ral-model uvm-register-model verilog vhdl
Last synced: 4 months ago
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- Host: GitHub
- URL: https://github.com/rggen/rggen-sample-testbench
- Owner: rggen
- License: mit
- Created: 2019-07-20T15:44:12.000Z (almost 7 years ago)
- Default Branch: master
- Last Pushed: 2026-02-04T00:58:26.000Z (4 months ago)
- Last Synced: 2026-02-04T12:57:17.749Z (4 months ago)
- Topics: systemverilog, uvm, uvm-ral-model, uvm-register-model, verilog, vhdl
- Language: VHDL
- Homepage: https://github.com/rggen/rggen
- Size: 711 KB
- Stars: 15
- Watchers: 3
- Forks: 5
- Open Issues: 1
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# RgGen Sample Testbench
This is an sample testbench to demonstrate integrating UVM RAL model generated by `RgGen` into UVM based testbench.
## Preparation
This env uses [flgen](https://github.com/pezy-computing/flgen) to generate *.f files which are given to simulator tools.
Therefore, you need to install the tool before using this env. See its repository for details.
## DUT
In this testbech, CSR modules generated by `RgGen` are used as DUT and there are three types of DUT:
* DUT with AMBA APB iterface
* https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/apb
* DUT with AMBA AXI4-Lite interface
* https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/axi4lite
* DUT with Avalon-MM interface
* https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/avalon
* DUT with wishbone interface
* https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/wishbone
* DUT with native interface
* https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/native
## Sample Testcases
This testbench inclues three sample testcases invoking pre-defined test sequences.
| Test Name | Test Sequence |
|:------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------|
| ral_hw_reset_test | [uvm_reg_hw_reset_seq](https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/files/reg/sequences/uvm_reg_hw_reset_seq-svh.html) |
| ral_bit_bash_test | [uvm_reg_bit_bash_seq](https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/files/reg/sequences/uvm_reg_bit_bash_seq-svh.html) |
| ral_access_test | [uvm_reg_access_seq](https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/files/reg/sequences/uvm_reg_access_seq-svh.html) |
## Usage
### Setup
This testbench depends on some submodules so you need to get them from GitHub repositries.
To do this, hit the command below on the root of this repositly.
```
$ cd rggen-sample-testbench
$ ./setup_submodules.sh
```
If execution of above commands failed you need to get them from GitHub repositlies directly and set some environment variables.
```
$ git clone https://github.com/taichi-ishitani/tue.git
$ export TUE_HOME=`pwd`/tue
$ git clone https://github.com/taichi-ishitani/tvip-common.git
$ export TVIP_COMMON_HOME=`pwd`/tvip-common
$ git clone https://github.com/taichi-ishitani/tvip-apb.git
$ export TVIP_APB_HOME=`pwd`/tvip-apb
$ git clone https://github.com/taichi-ishitani/tvip-axi.git
$ export TVIP_APB_HOME=`pwd`/tvip-axi
$ git clone https://github.com/rggen/rggen-sv-rtl.git
$ export RGGEN_SV_RTL_ROOT=`pwd`/rggen-sv-rtl
$ git clone https://github.com/rggen/rggen-sv-ral.git
$ export RGGEN_SV_RTL_ROOT=`pwd`/rggen-sv-ral
$ git clone https://github.com/rggen/rggen-verilog-rtl.git
$ export RGGEN_VERILOG_RTL_ROOT=`pwd`/rggen-verilog-rtl
$ git clone https://github.com/rggen/rggen-vhdl-rtl.git
$ export RGGEN_VHDL_RTL_ROOT=`pwd`/rggen-vhdl-rtl
```
### Run Simulation
Synopsys VCS simulator, Cadence Xcelium simulator, Metrics DSim simulator and AMD Vivado simulator are supported.
1. Move to the work directry
* for DUT with AMBA APB interfac
* `sim/apb/systemverilog`
* `sim/apb/verilog`
* `sim/apb/veryl`
* `sim/apb/vhdl`
* for DUT with AMBA AXI4-Lite interface
* `sim/axi4lite/systemverilog`
* `sim/axi4lite/verilog`
* `sim/axi4lite/veryl`
* `sim/axi4lite/vhdl`
* for DUT with Avalon-MM interface
* `sim/avalon/systemverilog`
* `sim/avalon/verilog`
* `sim/avalon/veryl`
* `sim/avalon/vhdl`
* for DUT with wishbone interface
* `sim/wishbone/systemverilog`
* `sim/wishbone/verilog`
* `sim/wishbone/veryl`
* `sim/wishbone/vhdl`
* for DUT with native interface
* `sim/native/systemverilog`
* `sim/native/verilog`
* `sim/native/veryl`
* `sim/native/vhdl`
2. Hit `make` command on the work directry
```
$ make
```
By default, all sample testcases will be execluted by VCS simulator.
If you want to use Xcelium, DSim or Vivado simulator, add `SIMULATOR` option to `makefile` command.
* For Xcelium:
```
$ make SIMULATOR=xcelium
```
* For DSim
```
$ make SIMULATOR=dsim
```
* For Vivado:
```
$ make SIMULATOR=vivado
```
If you want to execute an specific testcase then you need to give its name to `make` command like below.
```
$ make ral_bit_bash_test
```
The `GUI` option is to enable the inteructive debug environment.
To invoke the GUI frontend, give this option to `make` command like below.
* Frontend: DVE
```
$ make ral_bit_bash_test GUI=dve
```
* Frontend: Verdi
```
$ make ral_bit_bash_test GUI=verdi
```
* Frontend: Indago
```
$ make ral_bit_bash_test SIMULATOR=xcelium GUI=indago
```
* Frontend: Vivado
```
$ make ral_bit_bash_test SIMULATOR=vivado GUI=on
```
## Contact
You can post your questions, feedbacks, bug reports, etc. by using following ways.
* [GitHub Issue Tracker](https://github.com/rggen/rggen-sample-testbench/issues)
* [Discord](https://discord.com/invite/KWya83ZZxr)
* [Mailing List](https://groups.google.com/d/forum/rggen)
* [Mail](mailto:rggen@googlegroups.com)
## Copyright & License
Copyright © 2019-2026 Taichi Ishitani. This testbench is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.