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https://github.com/rinhizakura/riscv-emulator
A project for learning RISC-V architecture purpose
https://github.com/rinhizakura/riscv-emulator
c emulator riscv riscv-emulator
Last synced: about 2 months ago
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A project for learning RISC-V architecture purpose
- Host: GitHub
- URL: https://github.com/rinhizakura/riscv-emulator
- Owner: RinHizakura
- License: mit
- Created: 2021-01-27T17:18:44.000Z (almost 4 years ago)
- Default Branch: main
- Last Pushed: 2023-11-09T07:02:08.000Z (about 1 year ago)
- Last Synced: 2024-04-16T23:09:57.536Z (9 months ago)
- Topics: c, emulator, riscv, riscv-emulator
- Language: C
- Homepage:
- Size: 8.57 MB
- Stars: 22
- Watchers: 3
- Forks: 3
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# riscv-emulator
**(Note: This project is still on the process for completion!)**
The project is built to learn RISC-V architecture as the purpose for me. It mainly comes
from [rvemu](https://github.com/d0iasm/rvemu), which is a RISC-V emulator with
Rust implementation. Also, some of the idea of CPU implementation is borrowed from
[riscv_em](https://github.com/franzflasch/riscv_em).
The emulator now supports fully RV64I, M, Zicsr, and Zifencei instructions. Most of the RV64C
and some RV64A instructions are also supported.
## Build and Run
To build the emulator:
```
$ make
```
Although the instruction cache isn't an esstential component for our emulator, but it could
help to speed it with the fast path to decode an instruction! Note that the best
configuration for the number of cache set and cache way will require more experiment, now
they just simply set to 8 and 4. To build the emulator with I-cache:
```
$ make ICACHE=1
```
The emulator is also validated to run [xv6-riscv](https://github.com/mit-pdos/xv6-riscv),
which is a simple UNIX operating system. You can use the provided binary by the following
command directly:
```
$ make run-xv6
```
We also try to support running Linux on the emulator. Although it still need some work to boot
completly. You can take a try with the following command.
```
$ make run-linux
```
If you want to run your own binary, the binary file in raw or ELF format are both supported.
The emulator will check whether the input binary is under ELF format first, otherwise it will
take it as a raw binary. You should notice that the process of ELF parsing now could be
non-general and ugly, so feel free to report if you can't load your ELF binary! To load and
run your binary on the emulator:
```
$ ./build/emu --binary [--rfsimg ]
```
## Compliance Test
The [riscv-arch-test](https://github.com/riscv/riscv-arch-test) is applied to check if
implementing the specifications correctly. We can pass RV64I, RV64M,
and RV64C(except cebreak) now.
You'll need `riscof` to run the test. The following command could be use to simply
install it. Please take a look at [RISCOF document](https://riscof.readthedocs.io/en/stable/index.html)
if you find any problem when installing it.
```
$ pip3 install git+https://github.com/riscv/riscof.git
```
After installing `riscof`, You can run the compliance test by the following command.
```
$ make run-compliance
```
## Instruction Unit Test
The [riscv-tests](https://github.com/riscv-software-src/riscv-tests) is also applied to check
if implementing the specifications correctly. We can pass RV64UI, RV64UM, RV64UC and RV64UA
now. You can run the riscv-tests by the following command.
```
$ make run-riscv-tests
```