https://github.com/risclite/ARM9-compatible-soft-CPU-core

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
https://github.com/risclite/ARM9-compatible-soft-CPU-core

32-bit armv4 cpu verilog

Last synced: 2 months ago
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This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

• Host: GitHub
• URL: https://github.com/risclite/ARM9-compatible-soft-CPU-core
• Owner: risclite
• License: apache-2.0
• Created: 2018-10-14T12:39:18.000Z (over 6 years ago)
• Default Branch: master
• Last Pushed: 2020-10-14T07:26:51.000Z (over 4 years ago)
• Last Synced: 2024-11-07T01:50:03.646Z (3 months ago)
• Topics: 32-bit, armv4, cpu, verilog
• Language: Verilog
• Size: 101 MB
• Stars: 75
• Watchers: 6
• Forks: 32
• Open Issues: 3

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