https://github.com/rust-embedded/riscv

Low level access to RISC-V processors
https://github.com/rust-embedded/riscv

Last synced: 9 days ago
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Low level access to RISC-V processors

• Host: GitHub
• URL: https://github.com/rust-embedded/riscv
• Owner: rust-embedded
• Created: 2017-09-19T14:24:48.000Z (about 7 years ago)
• Default Branch: master
• Last Pushed: 2024-09-11T07:35:21.000Z (about 2 months ago)
• Last Synced: 2024-09-17T14:51:41.656Z (about 2 months ago)
• Language: Rust
• Homepage:
• Size: 1.05 MB
• Stars: 825
• Watchers: 31
• Forks: 160
• Open Issues: 15
• Metadata Files:
  • Readme: README.md
  • Code of conduct: CODE_OF_CONDUCT.md
  • Codeowners: .github/CODEOWNERS

Awesome Lists containing this project

• rust-embedded - `riscv` - level access to RISC-V processors - [](https://crates.io/crates/riscv) (Architecture support crates / RISC-V)
• awesome-embedded-rust - `riscv` - level access to RISC-V processors - [](https://crates.io/crates/riscv) (Architecture support crates / RISC-V)

README

        
# RISC-V crates

This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers:

* [`riscv`]: CPU registers access and intrinsics

* [`riscv-pac`]: Common traits to be implemented by RISC-V PACs

* [`riscv-peripheral`]: Interfaces for standard RISC-V peripherals

* [`riscv-rt`]: Startup code and interrupt handling

* [`riscv-semihosting`]: Semihosting for RISC-V processors

This project is developed and maintained by the [RISC-V team][team].

### Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the

work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any

additional terms or conditions.

## Code of Conduct

Contribution to this crate is organized under the terms of the [Rust Code of

Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises

to intervene to uphold that code of conduct.

[`riscv`]: https://crates.io/crates/riscv

[`riscv-pac`]: https://crates.io/crates/riscv-pac

[`riscv-peripheral`]: https://crates.io/crates/riscv-peripheral

[`riscv-rt`]: https://crates.io/crates/riscv-rt

[`riscv-semihosting`]: https://crates.io/crates/riscv-semihosting

[team]: https://github.com/rust-embedded/wg#the-risc-v-team

[CoC]: CODE_OF_CONDUCT.md