https://github.com/samiyaalizaidi/pipelined-risc-v-processor

A Pipelined RISC-V Processor with forwarding support and hazard detection.
https://github.com/samiyaalizaidi/pipelined-risc-v-processor

assembly computer-architecture pipelining processor processor-architecture risc-v verilog vivado

Last synced: 3 months ago
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A Pipelined RISC-V Processor with forwarding support and hazard detection.

• Host: GitHub
• URL: https://github.com/samiyaalizaidi/pipelined-risc-v-processor
• Owner: samiyaalizaidi
• Created: 2023-04-17T04:48:27.000Z (about 2 years ago)
• Default Branch: main
• Last Pushed: 2023-05-09T06:38:08.000Z (about 2 years ago)
• Last Synced: 2025-01-16T16:41:31.315Z (5 months ago)
• Topics: assembly, computer-architecture, pipelining, processor, processor-architecture, risc-v, verilog, vivado
• Language: Verilog
• Homepage:
• Size: 79.1 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Pipelined RISC-V Processor

This repository consists all the code for our Computer Architecture & Organizations's final project. All the code is written in Verilog HDL.

The processor sorts the following array of numbers in the descending order: {1, 5, 3, 4, 10, 22, 2, 3, 44} using the selection sort algorithm.