https://github.com/sanugiw/fpga
UA UART communication module using Verilog on a DE0-Nano FPGA with real-time serial data transfer, and verified functionality with a custom test bench.
https://github.com/sanugiw/fpga
fpga-programming modelsim systemverilog verilog-hdl
Last synced: 2 months ago
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UA UART communication module using Verilog on a DE0-Nano FPGA with real-time serial data transfer, and verified functionality with a custom test bench.
- Host: GitHub
- URL: https://github.com/sanugiw/fpga
- Owner: Sanugiw
- Created: 2025-05-23T07:29:47.000Z (11 months ago)
- Default Branch: main
- Last Pushed: 2025-05-25T12:17:41.000Z (11 months ago)
- Last Synced: 2025-10-06T20:57:14.252Z (7 months ago)
- Topics: fpga-programming, modelsim, systemverilog, verilog-hdl
- Homepage:
- Size: 3.49 MB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0