https://github.com/sergz72/fpga

FPGA related stuff
https://github.com/sergz72/fpga

assembler assembly-language bytecode-compiler cpu cyclone forth forth-cpu forth-language fpga fpga-programming gowin java java-cpu risc-v verilog

Last synced: 24 days ago
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FPGA related stuff

• Host: GitHub
• URL: https://github.com/sergz72/fpga
• Owner: sergz72
• License: mit
• Created: 2024-07-05T15:21:23.000Z (6 months ago)
• Default Branch: main
• Last Pushed: 2024-11-26T17:17:58.000Z (26 days ago)
• Last Synced: 2024-11-26T18:24:27.608Z (26 days ago)
• Topics: assembler, assembly-language, bytecode-compiler, cpu, cyclone, forth, forth-cpu, forth-language, fpga, fpga-programming, gowin, java, java-cpu, risc-v, verilog
• Language: Verilog
• Homepage:
• Size: 1.3 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

        
# FPGA projects

[Cpu16Lite](Cpu16Lite) - 16 bit cpu with 256 registers

[ForthCPU](ForthCPU) - CPU, designed to run code, compiled by Forth language compiler.

[JavaCPU](JavaCPU) - CPU, designed to run code, translated from Java bytecode.

[LedPmodTest](LedPmodTest) - simple Verilog code to test LED PMODs.

[Software](Software) - Various software related to my FPGA projects (compilers, translators, etc...).

[Tiny16](tiny16) - 16 bit cpu

[Tiny32](tiny32) - RV32I(M) core

[archived](archived) - archived projects

[boards](boards) - projects, related to specific FPGA boards.

[common](common) - common Verilog components

[unfinished](unfinished) - unfinished projects

[untested](untested) - some untested stuff