https://github.com/shashankvm/generic_systemverilog_designs_library
A library of useful, fully parameterized RTL designs implemented in SystemVerilog.
https://github.com/shashankvm/generic_systemverilog_designs_library
basic-learning digital-logic-design systemverilog
Last synced: about 1 month ago
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A library of useful, fully parameterized RTL designs implemented in SystemVerilog.
- Host: GitHub
- URL: https://github.com/shashankvm/generic_systemverilog_designs_library
- Owner: ShashankVM
- License: bsd-3-clause
- Created: 2021-02-14T14:52:23.000Z (about 5 years ago)
- Default Branch: main
- Last Pushed: 2022-03-06T13:22:54.000Z (almost 4 years ago)
- Last Synced: 2025-06-19T13:47:02.177Z (9 months ago)
- Topics: basic-learning, digital-logic-design, systemverilog
- Language: SystemVerilog
- Homepage:
- Size: 39.1 KB
- Stars: 6
- Watchers: 1
- Forks: 1
- Open Issues: 0