https://github.com/shehanmunasinghe/tinygpu

tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
https://github.com/shehanmunasinghe/tinygpu

computer-organization gpu hdl processor-design simd systemverilog

Last synced: 4 months ago
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tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog

• Host: GitHub
• URL: https://github.com/shehanmunasinghe/tinygpu
• Owner: shehanmunasinghe
• Created: 2020-10-02T11:42:52.000Z (over 5 years ago)
• Default Branch: main
• Last Pushed: 2021-07-14T07:31:38.000Z (over 4 years ago)
• Last Synced: 2025-03-15T10:11:23.581Z (11 months ago)
• Topics: computer-organization, gpu, hdl, processor-design, simd, systemverilog
• Language: SystemVerilog
• Homepage:
• Size: 1.23 MB
• Stars: 43
• Watchers: 4
• Forks: 9
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
# Predicated-SIMD Processor

Designing a **Predicated-SIMD(Single Instruction Multiple Data) Processor** for 2D Matrix Multiplication, under the **EN3030 Circuits and Systems** module.

This repository contains

* Python programs for simulation of programs written in assembly language of the proposed Instruction Set Architecture (ISA)

* SystemVerilog implementation of the hardware modules

* Evaluation script for validating the design against a 2D matrix multiplication task

## Processor Design

### Instruction Set Architecture (ISA)

![ISA](docs/images/ISA.png "ISA")

### Datapath

![datapath](docs/images/datapath.png "datapath")

### RTL Modules

The information about the RTL Modules can be found [here](./Verilog/_Info.md).

## How to Run the Project

### Requirements

* Python 3

    * Numpy

* IcarusVerilog

### ISA Simulation

Find instructions [here](./Simulator/_INSTRUCTIONS.md).

### SystemVerilog Simulation

Find instructions [here](./Verilog/_INSTRUCTIONS.md).

### Evaluation

    python3 Evaluation/evaluation_script.py