https://github.com/sinakarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
https://github.com/sinakarvandi/hardware-design-stack

asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls

Last synced: about 1 month ago
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The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

• Host: GitHub
• URL: https://github.com/sinakarvandi/hardware-design-stack
• Owner: SinaKarvandi
• License: mit
• Created: 2023-10-04T13:10:10.000Z (about 1 year ago)
• Default Branch: main
• Last Pushed: 2023-10-08T09:16:47.000Z (about 1 year ago)
• Last Synced: 2023-10-09T09:34:25.124Z (about 1 year ago)
• Topics: asic, asic-design, chisel, chisel3, fpga, gtkwave, modelsim, netlist, openlane, openram, verilator, verilog, vhdl, vitis, vitis-hls, vivado, vivado-hls
• Language: VHDL
• Homepage: https://rayanfam.com/topics/hardware-design-stack/
• Size: 46.9 KB
• Stars: 2
• Watchers: 1
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# Hardware Design Stack

Welcome to the repository for the source codes discussed in the blog post available at [https://rayanfam.com/topics/hardware-design-stack](https://rayanfam.com/topics/hardware-design-stack/).

## Description

Are you interested in delving into the fascinating world of hardware design? This repository is your gateway to exploring the intricacies of hardware design, from understanding fundamental concepts to hands-on experience with hardware description languages, synthesis, simulation, and more. In the blog post associated with this repository, we take you on a journey through the hardware design landscape, offering insights into various aspects, tools, and techniques that are crucial for designing and implementing hardware systems.

## Table of Contents

- Introduction

- Analog Signals/Protocols

- Digital Signals/Protocols

- Source Code

- Moore’s Law & Amdahl’s Law

- Terms

- Hardware Description Languages

- Generating Hardware Using Chisel

- C/C++ in Hardware Design

- Vitis HLS

- Simulating Codes

- Simulating HDL Code Using GTKWave or ModelSim

- Testing Codes in Chisel

- Testing HDL Codes Using Verilator

- Synthesising HDL Codes

- Programming Xilinx FPGAs Using Vivado

- Vivado Netlists

- The Memory

- Distributed RAMs in FPGAs

- Block RAM (BRAM) in FPGAs

- Static RAM (SRAM) in ASIC

- Elaborating ASIC Designs

- Building Hardware Layout (GDSII)

- Reverse Engineering Netlists

- Conclusion

- References