https://github.com/skpro-glitch/parallel_multiplier

Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.
https://github.com/skpro-glitch/parallel_multiplier

asic asic-design fpga fpga-programming multiplier parallel-multiplication register-transfer-level rtl rtl-design systemverilog systemverilog-test-bench verilog-hdl vlsi-design xilinx-vivado

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Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.

• Host: GitHub
• URL: https://github.com/skpro-glitch/parallel_multiplier
• Owner: SKpro-glitch
• License: mit
• Created: 2024-12-13T08:07:36.000Z (5 months ago)
• Default Branch: main
• Last Pushed: 2024-12-13T08:44:19.000Z (5 months ago)
• Last Synced: 2025-02-13T01:51:17.383Z (2 months ago)
• Topics: asic, asic-design, fpga, fpga-programming, multiplier, parallel-multiplication, register-transfer-level, rtl, rtl-design, systemverilog, systemverilog-test-bench, verilog-hdl, vlsi-design, xilinx-vivado
• Language: SystemVerilog
• Homepage:
• Size: 13.7 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# Parallel Multiplier




**Author:** Soham Kapur




**Description:** Implementation of a generalized Parallel Multiplier using Carry Save Adder with SystemVerilog and Xilinx Vivado. 




**Tools Used:** SystemVerilog HDL, Xilinx Vivado




**Concepts used:** Parameterization, Parallel Multiplier, Carry Save Adder




**Multiplier Schematic:** 4x4 multiplier




![image](https://github.com/user-attachments/assets/b64028a8-f875-4ddb-a9af-f5702b26bf18)




**Adder Row Schematic:** Individual instance of Intermediate Product module




![image](https://github.com/user-attachments/assets/71dfe993-168c-44d8-8bf0-0bca8460cf78)