https://github.com/skpro-glitch/riscv-processor-asic
This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.
https://github.com/skpro-glitch/riscv-processor-asic
asic asic-design asic-verification fpga hardware-designs open-source openlane openlane-flow processor-architecture processor-design risc-v riscv32 verilog verilog-hdl vlsi vlsi-design
Last synced: 3 months ago
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This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.
- Host: GitHub
- URL: https://github.com/skpro-glitch/riscv-processor-asic
- Owner: SKpro-glitch
- Created: 2024-09-16T02:41:32.000Z (10 months ago)
- Default Branch: main
- Last Pushed: 2025-04-04T04:12:22.000Z (3 months ago)
- Last Synced: 2025-04-04T05:19:56.229Z (3 months ago)
- Topics: asic, asic-design, asic-verification, fpga, hardware-designs, open-source, openlane, openlane-flow, processor-architecture, processor-design, risc-v, riscv32, verilog, verilog-hdl, vlsi, vlsi-design
- Language: Verilog
- Homepage:
- Size: 138 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# RISCV-Processor-ASIC
**Author:** Soham Kapur
**Description:** This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.