https://github.com/socxin/stm32u5a9

L3 R4: ST Cortex-M33 160MHz MCU
https://github.com/socxin/stm32u5a9

cortex-m33 mcu neo-chrom qitas st

Last synced: about 18 hours ago
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L3 R4: ST Cortex-M33 160MHz MCU

• Host: GitHub
• URL: https://github.com/socxin/stm32u5a9
• Owner: SoCXin
• Created: 2019-07-13T15:15:41.000Z (over 5 years ago)
• Default Branch: master
• Last Pushed: 2024-05-03T12:55:41.000Z (8 months ago)
• Last Synced: 2024-11-05T10:30:58.999Z (about 2 months ago)
• Topics: cortex-m33, mcu, neo-chrom, qitas, st
• Homepage:
• Size: 1.95 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • Funding: .github/FUNDING.yml

Awesome Lists containing this project

README

        
# [STM32U5A9](https://github.com/SoCXin/STM32U5A9)

* [ST](www.st.com)：[Cortex-M33](https://github.com/SoCXin/Cortex)

* [L3R4](https://github.com/SoCXin/Level)：160 MHz (655 CoreMark,4.09/MHz)

## [简介](https://github.com/SoCXin/STM32U5A9/wiki)

[STM32U5A9](https://www.st.com/zh/microcontrollers-microprocessors/stm32u5a9nj.html) 

### 关键特性

* 160 MHz Cortex-M33 

* 2.5 MB SRAM

* 2x 14-bit ADC 2.5Msps

* Neo-Chrom GPU(GPU2D),16-Kbyte DCACHE2

* Chrom-GRC (GFXMMU) allowing up to 20 % of graphic resources optimization

* MIPI® DSI host controller with two DSI lanes running at up to 500 Mbit/s each

* 2 Octo-SPI memory interfaces

* 16-bit HSPI memory interface up to 160 MHz

* 480 nA Standby mode with RTC

* 2 μA Stop 3 mode with 40-Kbyte SRAM

* 8.2 μA Stop 3 mode with 2.5-Mbyte SRAM

* 4.65 µA Stop 2 mode with 40-Kbyte SRAM

* 17.5 µA Stop 2 mode with 2.5-Mbyte SRAM

* 18.5 μA/MHz Run mode at 3.3 V

## [资源收录](https://github.com/SoCXin)

* [参考资源](src/)

* [参考文档](docs/)

* [参考工程](project/)

## [选型建议](https://github.com/SoCXin)

[STM32U5A9](https://github.com/SoCXin/STM32U5A9)