https://github.com/sofiavalos/verilog_ethernet_10g_pcs

Bloques y bancos de pruebas PCS para Ethernet 10G.
https://github.com/sofiavalos/verilog_ethernet_10g_pcs

ethernet pcs verilog

Last synced: 4 days ago
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Bloques y bancos de pruebas PCS para Ethernet 10G.

• Host: GitHub
• URL: https://github.com/sofiavalos/verilog_ethernet_10g_pcs
• Owner: sofiavalos
• License: mit
• Created: 2024-05-04T18:19:52.000Z (8 months ago)
• Default Branch: main
• Last Pushed: 2024-08-23T13:11:52.000Z (5 months ago)
• Last Synced: 2024-11-09T20:14:18.754Z (2 months ago)
• Topics: ethernet, pcs, verilog
• Language: Verilog
• Homepage: https://ethernet10g.netlify.app/10-gbase/pcs/eth-phy-10g/
• Size: 88.9 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

        
 Ethernet 10GBASE PCS 




   



## Repositorio

La base del repositorio son los módulos proporcionados por [Alex Forenchich](https://github.com/alexforencich/verilog-ethernet) en su propio repositorio.

## Documentación

El bloque PCS se encuentra estructurado de la siguiente manera:

```

eth_phy_10g

  └── eth_phy_10g_rx - eth_phy_10g_rx_inst

      ├── eth_phy_10g_rx_if - eth_phy_10g_rx_if_inst

      │   ├── lfsr - descrambler_inst

      │   ├── lfsr - prbs31_check_inst

      │   ├── eth_phy_10g_rx_frame_sync - eth_phy_10g_rx_frame_sync_inst

      │   ├── eth_phy_10g_rx_ber_mon - eth_phy_10g_rx_ber_mon_inst

      │   └── eth_phy_10g_rx_watchdog - eth_phy_10g_rx_watchdog_inst

      └── xgmii_baser_dec_64 - xgmii_baser_dec_inst

  └── eth_phy_10g_tx - eth_phy_10g_tx_inst

      ├── xgmii_baser_enc_64 - xgmii_baser_enc_inst

      └── eth_phy_10g_tx_if - eth_phy_10g_tx_if_inst

          ├── lfsr - scrambler_inst

          └── lfsr - prbs31_gen_inst

```

Para obtener más información detallada sobre los bloques PCS, consulta la [documentación detallada en la Wiki](https://github.com/sofiavalos/Ethernet_10g_PCS/wiki/Bloques-PCS).