https://github.com/stavros/multiplier4bit

A 4bit Multiplier in VHDL
https://github.com/stavros/multiplier4bit

fpga full-adder half-adder vhdl vhdl-code vhdl-examples

Last synced: about 1 month ago
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A 4bit Multiplier in VHDL

• Host: GitHub
• URL: https://github.com/stavros/multiplier4bit
• Owner: Stavros
• Created: 2020-02-03T12:50:51.000Z (about 5 years ago)
• Default Branch: master
• Last Pushed: 2020-02-03T16:51:40.000Z (about 5 years ago)
• Last Synced: 2025-01-18T02:27:40.998Z (3 months ago)
• Topics: fpga, full-adder, half-adder, vhdl, vhdl-code, vhdl-examples
• Language: VHDL
• Size: 2.94 MB
• Stars: 3
• Watchers: 3
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Multiplier4bit

A 4bit Multiplier in VHDL 

## Information

This is a VHDL project for DSD-I1* a Cyclone IV FPGA built in Quartus 18.1 to build a 2 x 4bit number multiplier using Full Adders and Half Adders.

**Diagram**:  

![Diagram](./Multiplier4bit.jpg)

**Behavioral VHDL code**: Multiplier4bit.vhd  

**Testbench VHDL code**: Multiplier4bit_tb.vhd  

**ModelSim**:  

![ModelSim](./Multiplier4bit_modelsim.jpg)

**FPGA**:  

![FPGA](./Multiplier4bit_fpga.jpg)

*Note: DSD-i1: A Mixed Functionality Development Board Geared Towards Digital Systems Design Education [DOI:10.1109/DSD.2019.00032](https://www.researchgate.net/deref/http%3A%2F%2Fdx.doi.org%2F10.1109%2FDSD.2019.00032?_sg%5B0%5D=v-cnN-1Q246lx6ZElyyd_L2GLjVH2cDblXKnupqF6zBTWGsRmigTw_ho2UEIExompd-pfg1aXKe2HxtKhm8yTj_qKA.RFCrYuolSv1xRRtksL0NU8xa-sfrV6ZTsQm8Z6Ge2xh6ypvMKM0sHAtBECzdcRJoFOjJpYWyh5DrIrnMCZrsYA)

## Licence

Copyright (c) 2019 Stavros Kalapothas (aka Stevaras) .

It is free software, and may be redistributed under the terms of the GNU Licence.