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https://github.com/styczynski/fpga-verilog
Collection of my projects that was made as a part of Warsaw University FPGA course
https://github.com/styczynski/fpga-verilog
fpga fpga-board fpga-programming hardware uart verilog vga
Last synced: 7 days ago
JSON representation
Collection of my projects that was made as a part of Warsaw University FPGA course
- Host: GitHub
- URL: https://github.com/styczynski/fpga-verilog
- Owner: styczynski
- License: mit
- Created: 2019-01-15T12:21:19.000Z (about 6 years ago)
- Default Branch: master
- Last Pushed: 2019-02-05T21:46:16.000Z (almost 6 years ago)
- Last Synced: 2024-11-15T16:17:20.040Z (2 months ago)
- Topics: fpga, fpga-board, fpga-programming, hardware, uart, verilog, vga
- Language: Verilog
- Homepage:
- Size: 441 KB
- Stars: 6
- Watchers: 2
- Forks: 0
- Open Issues: 0