https://github.com/sysprog21/ca2023-lab3

Lab3: Construct a single-cycle CPU with Chisel
https://github.com/sysprog21/ca2023-lab3

Last synced: 4 months ago
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Lab3: Construct a single-cycle CPU with Chisel

• Host: GitHub
• URL: https://github.com/sysprog21/ca2023-lab3
• Owner: sysprog21
• License: mit
• Created: 2023-11-07T00:23:02.000Z (over 2 years ago)
• Default Branch: main
• Last Pushed: 2023-11-20T10:22:07.000Z (over 2 years ago)
• Last Synced: 2025-05-08T23:54:09.839Z (about 1 year ago)
• Language: Scala
• Size: 30.3 KB
• Stars: 18
• Watchers: 4
• Forks: 60
• Open Issues: 1
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# Construct a single-cycle RISC-V CPU with Chisel

> [!WARNING]

> Please be aware that the Scala code in this repository is not entirely complete, as the instructor has omitted certain sections for students to work on independently.

## Development Objectives

Our goal is to create a RISC-V CPU that prioritizes simplicity while assuming a foundational understanding of digital circuits and the C programming language among its readers. The CPU should strike a balance between simplicity and sophistication, and we intend to maximize its functionality. This project encompasses the following key aspects, which will be prominently featured in the technical report:

* Implementation in Chisel.

* RV32I instruction set support.

* Execution of programs compiled from the C programming language.