https://github.com/t-k-233/risc-v-single-cycle-cpu

RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel
https://github.com/t-k-233/risc-v-single-cycle-cpu

chisel logisim risc-v verilog

Last synced: 15 days ago
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RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel

• Host: GitHub
• URL: https://github.com/t-k-233/risc-v-single-cycle-cpu
• Owner: T-K-233
• License: mit
• Created: 2020-04-17T08:12:36.000Z (about 5 years ago)
• Default Branch: main
• Last Pushed: 2025-02-06T07:39:05.000Z (2 months ago)
• Last Synced: 2025-02-06T08:34:27.061Z (2 months ago)
• Topics: chisel, logisim, risc-v, verilog
• Language: Verilog
• Homepage:
• Size: 16.7 MB
• Stars: 429
• Watchers: 10
• Forks: 45
• Open Issues: 1
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# RISC-V Single Cycle CPU

![Cover Image](docs/cover.jpg)

---

![Result Image](docs/result.jpg)

## Notes

- Single page version can achieve ~300 Hz clock rate on a i7-6700K computer.

## Terms and Conditions

The software [Logisim-evoluion](https://github.com/logisim-evolution/logisim-evolution) is released under the terms of the [GNU GENERAL PUBLIC LICENSE (GPL)](https://github.com/logisim-evolution/logisim-evolution/blob/master/LICENSE.md). For your convenience, the jar file is included in this repository in accordance with the redistribution guideline of the GPL-3.0 license agreement.

This project is under MIT License.