https://github.com/taichi-ishitani/tvip-axi

AMBA AXI VIP
https://github.com/taichi-ishitani/tvip-axi

amba amba-axi axi axi4 systemverilog uvm vip

Last synced: 7 months ago
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AMBA AXI VIP

• Host: GitHub
• URL: https://github.com/taichi-ishitani/tvip-axi
• Owner: taichi-ishitani
• License: apache-2.0
• Created: 2018-09-22T14:43:33.000Z (about 7 years ago)
• Default Branch: master
• Last Pushed: 2024-06-28T07:50:07.000Z (over 1 year ago)
• Last Synced: 2025-02-05T12:43:42.364Z (9 months ago)
• Topics: amba, amba-axi, axi, axi4, systemverilog, uvm, vip
• Language: SystemVerilog
• Size: 153 KB
• Stars: 373
• Watchers: 16
• Forks: 108
• Open Issues: 8
• Metadata Files:
  • Readme: README.md
  • Funding: .github/FUNDING.yml
  • License: LICENSE

Awesome Lists containing this project

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README

          
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# TVIP-AXI

TVIP-AXI is an UVM package of AMBA AXI4 VIP.

## Feature

* Master and slave agent

* Support AXI4 and AXI4-Lite protocols

* Highly configurable

    * address width

    * data width

    * ID width

    * etc.

* Support delayed write data and response

* Support gapped write data and read response

* Response ordering

    * in-order response

    * out of order response

* Support read interleave

* Include UVM RAL adapter and predictor

## Sample Environment

The sample environment is included. The execution procedure is as following.

### Preparation

Before executing the sample environment, you need to clone submodules. Hit command below on the root directory of TVIP-AXI.

    $ ./setup_submodules.sh

### Execution

To execute the sample environment, hit command below on the `sample/work` directory.

    $ make

Then, all sample test cases will be executed by using Synopsys VCS simulator.

If you want to use Cadence Xcelium simulator, hit command below.

    $ make SIMULATOR=xcelium

If you want to execute a test case individually, hit command below.

    $ make NAME_OF_TEST_CASE

Followings are available test cases:

* default

* request_delay

    * sample for delayed request

    * sample for gapped write data

* response_delay

    * sample for delayed response

    * sample for gapped read response

* out_of_order_response

    * sample for out of order response

* read_interleave

    * sample for read interleave

### Supported Simulator

Supported simulators are below:

* Synopsys VCS

* Cadence Xcelium

    * `-warn_multiple_driver` option may be needed to avoid `E,ICDCBA` error

* Metrics DSim Simulator

## Contact

If you have any questions, problems, feedbacks, etc., you can post them on following ways:

* [GitHub Issue Tracker](https://github.com/taichi-ishitani/tvip-axi/issues)

* [Chat room](https://gitter.im/taichi-ishitani/tvip-axi)

## Copyright

Copyright (C) 2018 Taichi Ishitani.

TVIP-AXI is licensed under the Apache-2.0 license. See [LICENSE](LICENSE) for further details.