https://github.com/theema-dev/microrisc

Simple 16-bit RISC processor with a 5-stage pipeline architecture
https://github.com/theema-dev/microrisc

Last synced: 11 months ago
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Simple 16-bit RISC processor with a 5-stage pipeline architecture

• Host: GitHub
• URL: https://github.com/theema-dev/microrisc
• Owner: theEMA-dev
• License: mit
• Created: 2025-01-02T21:46:45.000Z (over 1 year ago)
• Default Branch: main
• Last Pushed: 2025-01-19T20:04:02.000Z (over 1 year ago)
• Last Synced: 2025-01-19T20:35:17.726Z (over 1 year ago)
• Language: Verilog
• Homepage:
• Size: 94.7 KB
• Stars: 0
• Watchers: 1
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# microRISC

microRISC is a 16-bit RISC processor featuring a 5-stage pipeline architecture. It was designed to meet the [specifications](https://online-learning2024-2025.gidatarim.edu.tr/pluginfile.php/18890/mod_assign/introattachment/0/CORG_Project_II.pdf?forcedownload=1) of the 2024-2025 Fall Semester Computer Architecture Course Project II.

## Contents

### Phase 1: *Processor Design*

- [Instruction Set Design](docs/design/instructions.md)

- [Full Circuit Design](docs/stages.png)

- [Files]()

### Phase 2: *Simulator Development*

- [Installation](docs/simulator/installation)

- [Building from Source]()

### Phase 3: *Verilog Implementation* 

> Work in Progress