https://github.com/thomasafroo/simple-risc-machine
Implements a RISC processor that executes a set of ARMv7 instructions.
https://github.com/thomasafroo/simple-risc-machine
risc simulation synthesis systemverilog
Last synced: over 1 year ago
JSON representation
Implements a RISC processor that executes a set of ARMv7 instructions.
- Host: GitHub
- URL: https://github.com/thomasafroo/simple-risc-machine
- Owner: thomasafroo
- Created: 2024-11-04T04:40:53.000Z (over 1 year ago)
- Default Branch: main
- Last Pushed: 2025-01-12T20:25:13.000Z (over 1 year ago)
- Last Synced: 2025-01-21T20:19:00.565Z (over 1 year ago)
- Topics: risc, simulation, synthesis, systemverilog
- Language: SystemVerilog
- Homepage:
- Size: 420 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
# Simple RISC Machine
This project implements a Reduced Instruction Set Computer (RISC) using SystemVerilog and can be tested using the Intel DE1-SoC development board.
The RISC machine can execute a set of instructions from the ARMv7 Instruction Set Architecture (ISA). It contains a datapath, finite state machine controller, and support for read-write memory.
This project was done in collaboration with my lab partner, Jackson Rockford, for CPEN 211: Introduction to Microcomputers.
Important: viewers should be mindful of the Academic Integrity Policy for CPEN 211 and UBC ECE.