https://github.com/thotypous/keccak-bsv

Bluespec SystemVerilog implementation of the Keccak primitive (SHA-3)
https://github.com/thotypous/keccak-bsv

bluespec cryptography hardware-designs keccak sha3

Last synced: about 1 month ago
JSON representation

Bluespec SystemVerilog implementation of the Keccak primitive (SHA-3)

• Host: GitHub
• URL: https://github.com/thotypous/keccak-bsv
• Owner: thotypous
• Created: 2015-12-27T01:00:32.000Z (about 9 years ago)
• Default Branch: master
• Last Pushed: 2015-12-27T22:12:19.000Z (about 9 years ago)
• Last Synced: 2023-06-16T21:15:58.663Z (over 1 year ago)
• Topics: bluespec, cryptography, hardware-designs, keccak, sha3
• Language: Bluespec
• Size: 210 KB
• Stars: 2
• Watchers: 3
• Forks: 2
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

        
# keccak-bsv

This is an almost literal translation of

[Keccak's reference VHDL implementation](http://keccak.noekeon.org/KeccakVHDL-3.1.zip)

mid-range core to the Bluespec SystemVerilog (BSV) language. Our goals are:

 * Easier integration with Bluespec and/or Verilog projects, specially when simulating with

   iverilog, whose support for mixed VHDL/Verilog simulation is still at early stages.

 * Be easier to understand and customize. As Bluespec is more flexible for static elaboration

   than VHDL, our code is more compact although it implements the same architecture.

## Building

Typing `make` will test the implementation against the test vectors (using Bluesim) and

subsequently build the `mkKeccak.v` hardware core.

## Synthesis comparison

To prove that our implementation is equivalent to the reference implementation,

we synthesized both implementations (for NumSlices=32) several times targeting an

Altera Cyclone V device (5CSEMA5F31C6), varying the Quartus II fitter seed each time.

The figure below presents histograms for the clock frequency and logic utilization

obtained by each implementation.

![Synthesis results](http://thotypous.github.io/keccak-bsv/synthesis.svg)

The reference implementation (VHDL) tends to achieve a slightly higher clock frequency,

whereas our implementation (BSV) occupies somewhat less area. Overall, both

implementations produce similar results, as expected.