https://github.com/tiagosr/gategen
Racket-based hardware definition DSL for generating gateware for FPGAs, ASICs and the like
https://github.com/tiagosr/gategen
asic-design dsl fpga fpga-programming hdl racket racket-languages
Last synced: 3 months ago
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Racket-based hardware definition DSL for generating gateware for FPGAs, ASICs and the like
- Host: GitHub
- URL: https://github.com/tiagosr/gategen
- Owner: tiagosr
- Created: 2023-08-24T10:17:11.000Z (over 2 years ago)
- Default Branch: main
- Last Pushed: 2023-11-28T21:56:54.000Z (over 2 years ago)
- Last Synced: 2024-01-26T19:00:35.478Z (about 2 years ago)
- Topics: asic-design, dsl, fpga, fpga-programming, hdl, racket, racket-languages
- Language: Racket
- Homepage:
- Size: 16.6 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files: