https://github.com/trcwm/fptool

Compiler for generating fixed-point logic using VHDL
https://github.com/trcwm/fptool

arithmetic fixed-point hdl signal-processing vhdl

Last synced: about 2 months ago
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Compiler for generating fixed-point logic using VHDL

• Host: GitHub
• URL: https://github.com/trcwm/fptool
• Owner: trcwm
• License: gpl-2.0
• Created: 2016-05-09T13:50:22.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2024-01-07T00:38:34.000Z (12 months ago)
• Last Synced: 2024-01-07T18:46:33.193Z (12 months ago)
• Topics: arithmetic, fixed-point, hdl, signal-processing, vhdl
• Language: C++
• Homepage:
• Size: 221 KB
• Stars: 7
• Watchers: 3
• Forks: 0
• Open Issues: 1
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# FPTOOL README

## A compiler for generating fixed-point VHDL code.

### Niels A. Moseley

The fixed-point tool (FPTOOL) takes mathematical expressions and fixed-point input variable definitions, and transforms them into VHDL (or verilog in the future). The compiler takes care of the precision/width of each intermediate result to avoid overflows.

It is designed to be most useful for digital signal processing arithmetic running in a single clock domain.

The compiler can generate multipliers with Canonical Signed Digit (CSD) constants, leading to area-efficient implementations.

Assumptions:

- all variables are SIGNED.

- all intermediate results are scaled to avoid overflow.

- all shift operators are of the arithmetic type and don't drop bits. (SHIFT OPERATION UNSUPPORTED)

- division is unsupported: multiply by 1/x.

- you know what you're doing: optimizations are not done (for now).

- Q(n,m) has 'm' factional bits and 'n' integer bits.

- the number of bits in a Q(n,m) is n+m.

- Q(1,7) has a range of [-1/128 .. 1/127], i.e. it can't represent 1.0 exactly.

Built-in functions:

- saturate(x,n,m) saturates variable 'x' to fit it into a Q(n,m) variable. (STILL UNSUPPORTED)

- truncate(x,n,m) removes (or adds) bits to variable 'x' so it becomes Q(n,m).

Operators:

- regular arithmetic: '+' '-' '*'

- line comment: '%'

- division operator is accepted but code for it will no be generated.

Current project state:

- Lexer is working.

- Parser can check the grammar (Except <<, >>, <<<, >>> and saturate) and build an abstract syntax tree.

- VHDL code generator is working (except for division operator)

- CSD expansion is working.

- Don't use it for production unless you test the output thoroughly!!

## Building

Load the project file (.pro) into [QtCreator](https://www.qt.io/ide/), configure the project for your compiler, then select Build->Build All.

## Command line options

- "-o VHDLFILENAME" to generate VHDL source code.

- "-g DOTFILENAME" to generate Graphviz/Dot formatted AST dump.

- "-L LOGFILE" to write the output to a log file.

- "-V" to enable verbose output.

- "-d" to enable debug output.

## Internal program flow

* The input file is read by the lexer. It produces a list of tokens.

* The parser analyses the tokens to check the syntax and collect data on variables/identifiers etc. It produces an abstract syntax tree (AST).

* The AST is transformed to a single-static-assigment (SSA) form, i.e. a list of simple assignments.

* Several micro passes (transformations) are performed on the SSA to remove the more complex commands and/or operands, such as multiplcations by a canonical signed digit constant.

* Finally, the VHDL code generate takes the final SSA list and transforms it into VHDL statements and associated documentation.

License: GPL v2.