https://github.com/ubaidrmn/risc-v-assembly
RISC-V assembly code I wrote as part of my COAL course at UIT University.
https://github.com/ubaidrmn/risc-v-assembly
assembly-language processor-architecture riscv rv32i
Last synced: 3 months ago
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RISC-V assembly code I wrote as part of my COAL course at UIT University.
- Host: GitHub
- URL: https://github.com/ubaidrmn/risc-v-assembly
- Owner: ubaidrmn
- Created: 2023-08-26T02:14:08.000Z (almost 2 years ago)
- Default Branch: main
- Last Pushed: 2023-08-26T02:46:31.000Z (almost 2 years ago)
- Last Synced: 2025-04-02T06:19:17.669Z (3 months ago)
- Topics: assembly-language, processor-architecture, riscv, rv32i
- Homepage:
- Size: 14.6 KB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# riscv-assembly
This repository includes RISC-V assembly code I wrote as part of my COAL course at UIT University. The `processor-design.circ` is a logisim file that includes a RV32I processor design with I,R,B, and S type instructions designed by me for the final exam.