https://github.com/ucb-bar/mada
Agile FPGA SoC design with Chisel and Mill.
https://github.com/ucb-bar/mada
chisel fpga millbuild
Last synced: about 2 months ago
JSON representation
Agile FPGA SoC design with Chisel and Mill.
- Host: GitHub
- URL: https://github.com/ucb-bar/mada
- Owner: ucb-bar
- License: mit
- Created: 2024-12-04T23:45:41.000Z (over 1 year ago)
- Default Branch: main
- Last Pushed: 2025-05-12T19:43:52.000Z (11 months ago)
- Last Synced: 2025-05-12T20:49:44.708Z (11 months ago)
- Topics: chisel, fpga, millbuild
- Language: Verilog
- Homepage:
- Size: 4.02 MB
- Stars: 2
- Watchers: 10
- Forks: 0
- Open Issues: 1
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# MaDa
## Getting Started
This project uses Mill as the Scala build tool. A ready-to-run script is provided as `/toolchains/mill`. To invoke mill directly, do
```bash
./toolchains/mill
```
The directory structure is organized in standalone packages. When running build flow, both the package name and the config name need to be provided:
```bash
make verilog PACKAGE=delta-soc MODULE=delta.MlpPolicyRunner
```
## Build Bitstream
```bash
make bitstream CONFIG=ExampleArty100TShell
```
## TODOs
- [ ] Better way of doing clock domain
- [ ] Fix Chipyard IP