https://github.com/ucb-bar/mada

Agile FPGA SoC design with Chisel and Mill.
https://github.com/ucb-bar/mada

chisel fpga millbuild

Last synced: about 1 month ago
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Agile FPGA SoC design with Chisel and Mill.

• Host: GitHub
• URL: https://github.com/ucb-bar/mada
• Owner: ucb-bar
• License: mit
• Created: 2024-12-04T23:45:41.000Z (6 months ago)
• Default Branch: main
• Last Pushed: 2025-05-03T00:48:24.000Z (about 2 months ago)
• Last Synced: 2025-05-03T01:46:24.284Z (about 2 months ago)
• Topics: chisel, fpga, millbuild
• Language: Verilog
• Homepage:
• Size: 2.93 MB
• Stars: 2
• Watchers: 10
• Forks: 0
• Open Issues: 1
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# MaDa

## Install Mill

```bash

./scripts/install-mill.sh

```

## Build Example

```bash

make verilog CONFIG=ExampleArty100TShell

```

## Build Bitstream

```bash

make bitstream CONFIG=ExampleArty100TShell

```

## TODOs

- [ ] Better way of doing clock domain

- [ ] Fix Chipyard IP