https://github.com/udxs/hdl-vlsi-exprs
A collection of select Verilog/Innovus (GDS2-only) experiments
https://github.com/udxs/hdl-vlsi-exprs
Last synced: 3 months ago
JSON representation
A collection of select Verilog/Innovus (GDS2-only) experiments
- Host: GitHub
- URL: https://github.com/udxs/hdl-vlsi-exprs
- Owner: UDXS
- Created: 2021-10-21T04:26:24.000Z (over 4 years ago)
- Default Branch: master
- Last Pushed: 2022-08-31T11:55:37.000Z (almost 4 years ago)
- Last Synced: 2025-01-19T18:14:10.093Z (over 1 year ago)
- Language: SystemVerilog
- Size: 527 KB
- Stars: 1
- Watchers: 2
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
# HDL/VLSI Experiments
A collection of Verilog/Innovus experiments.
## ASQRT
Flexible 32-bit square-root implementation. Implemented with Cadence Genus/Innovus and FreePDK45. Lacking formal verification.
## asterix-emu
Simple SPI-to-UART bridge emulating the Sharp LS013B7DH05 MiP display for smartwatch development purposes
with the Asterix RebbleOS platform and the Nordic nRF52840DK. There is a really small serial reader program
in asterix-emu/viewer.
## aTwo
Simple 8-bit CPU using someone else's ISA. Implemented with Cadence Genus/Innovus and FreePDK45. Lacking any verification.