https://github.com/ultraembedded/core_dbg_bridge

UART -> AXI Bridge
https://github.com/ultraembedded/core_dbg_bridge

axi4 fpga uart verilog

Last synced: about 2 months ago
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UART -> AXI Bridge

• Host: GitHub
• URL: https://github.com/ultraembedded/core_dbg_bridge
• Owner: ultraembedded
• License: lgpl-2.1
• Created: 2019-08-11T11:01:15.000Z (over 5 years ago)
• Default Branch: master
• Last Pushed: 2021-07-01T16:41:44.000Z (over 3 years ago)
• Last Synced: 2024-05-02T06:17:38.254Z (8 months ago)
• Topics: axi4, fpga, uart, verilog
• Language: Verilog
• Size: 21.5 KB
• Stars: 45
• Watchers: 5
• Forks: 16
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
### UART -> AXI Debug Bridge

Github:   [http://github.com/ultraembedded/cores](https://github.com/ultraembedded/cores/tree/master/dbg_bridge)

This component provides a bridge from a standard UART interface (8N1) to a AXI4 bus master & GPIO interface.  

This can be very useful for FPGA dev boards featuring a FTDI UART interface where loading memories, peeking, poking SoC state is required.

##### Testing

Used extensively on various Xilinx FPGAs over the years.

##### Configuration

* CLK_FREQ - Clock (clk_i) frequency (in Hz).

* UART_SPEED - UART baud rate (bps)

* AXI_ID - AXI ID to be used for transactions

##### Software

Included python based utils provide peek and poke access, plus binary load / dump support.

Examples:

```

# Read a memory location (0x0)

./sw/peek.py -d /dev/ttyUSB1 -b 115200 -a 0x0

# Write a memory word (0x0 = 0x12345678)

./sw/poke.py -d /dev/ttyUSB1 -b 115200 -a 0x0 -v 0x12345678

```