https://github.com/ultraembedded/core_usb_bridge

USB -> AXI Debug Bridge
https://github.com/ultraembedded/core_usb_bridge

axi4-lite fpga usb usb-cdc verilog

Last synced: 10 days ago
JSON representation

USB -> AXI Debug Bridge

• Host: GitHub
• URL: https://github.com/ultraembedded/core_usb_bridge
• Owner: ultraembedded
• License: lgpl-2.1
• Created: 2019-07-20T17:55:08.000Z (over 5 years ago)
• Default Branch: master
• Last Pushed: 2021-06-05T15:49:06.000Z (over 3 years ago)
• Last Synced: 2024-11-12T22:16:51.258Z (2 months ago)
• Topics: axi4-lite, fpga, usb, usb-cdc, verilog
• Language: Verilog
• Size: 22.5 KB
• Stars: 35
• Watchers: 8
• Forks: 9
• Open Issues: 0

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