https://github.com/ultraembedded/cores

Various HDL (Verilog) IP Cores
https://github.com/ultraembedded/cores

asic audio fpga i2s rtl sdram spi sram uart usb verilator verilog verilog-components verilog-hdl

Last synced: 2 months ago
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Various HDL (Verilog) IP Cores

• Host: GitHub
• URL: https://github.com/ultraembedded/cores
• Owner: ultraembedded
• Created: 2015-05-30T17:00:07.000Z (almost 11 years ago)
• Default Branch: master
• Last Pushed: 2021-07-01T16:43:34.000Z (almost 5 years ago)
• Last Synced: 2025-03-01T10:25:37.178Z (about 1 year ago)
• Topics: asic, audio, fpga, i2s, rtl, sdram, spi, sram, uart, usb, verilator, verilog, verilog-components, verilog-hdl
• Language: Verilog
• Homepage:
• Size: 211 KB
• Stars: 745
• Watchers: 50
• Forks: 218
• Open Issues: 3

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