https://github.com/ultraembedded/cores

Various HDL (Verilog) IP Cores
https://github.com/ultraembedded/cores

asic audio fpga i2s rtl sdram spi sram uart usb verilator verilog verilog-components verilog-hdl

Last synced: 3 months ago
JSON representation

Various HDL (Verilog) IP Cores

• Host: GitHub
• URL: https://github.com/ultraembedded/cores
• Owner: ultraembedded
• Created: 2015-05-30T17:00:07.000Z (over 9 years ago)
• Default Branch: master
• Last Pushed: 2021-07-01T16:43:34.000Z (over 3 years ago)
• Last Synced: 2024-06-15T23:35:49.683Z (5 months ago)
• Topics: asic, audio, fpga, i2s, rtl, sdram, spi, sram, uart, usb, verilator, verilog, verilog-components, verilog-hdl
• Language: Verilog
• Homepage:
• Size: 211 KB
• Stars: 648
• Watchers: 47
• Forks: 201
• Open Issues: 3

Awesome Lists containing this project

• StarryDivineSky - ultraembedded/cores: Various HDL (Verilog) IP Cores