https://github.com/ultraembedded/cores

Various HDL (Verilog) IP Cores
https://github.com/ultraembedded/cores

asic audio fpga i2s rtl sdram spi sram uart usb verilator verilog verilog-components verilog-hdl

Last synced: about 1 month ago
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Various HDL (Verilog) IP Cores

• Host: GitHub
• URL: https://github.com/ultraembedded/cores
• Owner: ultraembedded
• Created: 2015-05-30T17:00:07.000Z (over 9 years ago)
• Default Branch: master
• Last Pushed: 2021-07-01T16:43:34.000Z (over 3 years ago)
• Last Synced: 2024-11-10T00:32:59.919Z (about 1 month ago)
• Topics: asic, audio, fpga, i2s, rtl, sdram, spi, sram, uart, usb, verilator, verilog, verilog-components, verilog-hdl
• Language: Verilog
• Homepage:
• Size: 211 KB
• Stars: 707
• Watchers: 48
• Forks: 215
• Open Issues: 3

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