https://github.com/ultraembedded/openlogicbit

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
https://github.com/ultraembedded/openlogicbit

altera-fpga digital-signal-analyzer fpga ftdi2232h ftdi232h lattice-fpga logic-analyzer verilog xilinx-fpga

Last synced: 5 days ago
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Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

• Host: GitHub
• URL: https://github.com/ultraembedded/openlogicbit
• Owner: ultraembedded
• License: apache-2.0
• Created: 2021-06-20T22:13:33.000Z (over 3 years ago)
• Default Branch: main
• Last Pushed: 2021-06-24T19:24:26.000Z (over 3 years ago)
• Last Synced: 2024-05-02T06:17:41.057Z (7 months ago)
• Topics: altera-fpga, digital-signal-analyzer, fpga, ftdi2232h, ftdi232h, lattice-fpga, logic-analyzer, verilog, xilinx-fpga
• Language: Verilog
• Homepage:
• Size: 606 KB
• Stars: 97
• Watchers: 8
• Forks: 12
• Open Issues: 2
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# open-logic-bit

*Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.*

Github: [https://github.com/ultraembedded/openlogicbit](https://github.com/ultraembedded/openlogicbit)

![Demo-uart](docs/pulseview_uart.png)

## Aims

A logic analyzer project which aims to provide reliable, high speed (100MHz+), large capture depth, open-source gateware that can be used on a FPGA development board you already own, or as replacement gateware for commercial logic analysers that do not work with open-source tools such as [sigrok](https://sigrok.org/).

This project aims to support FPGA boards with 10's MBs of capture memory (such as DDR3), which also have high-speed USB interfaces from which to download the captured data.

There are a number of other open-source logic analyzer projects, but these mostly focus on using limited internal FPGA memories (embedded block RAMs), and low-performance host interfaces (UART).

## Features

* 16, 24, 32 input channels supported.

* Run-length encoded (RLE) compression to extend the sample buffer depth.

* Support for boards with large memories (DDR, SDRAM).

* Up to 32 triggers supporting edge, level, value match modes.

* Support for boards with FTDI sync FIFO mode support (FT232H, FT2232H).

* Support for external clock sources.

* Continuous or one-shot capture modes.

* libsigrok support available (enabling support for Sigrok, Pulseview).

*A screenshot of Sigrok capturing a SPDIF signal at 100MHz with open-logic-bit running on a Digilent Digital Discovery;*

![Demo-spdif](docs/pulseview_spdif.png)

## Supported Boards

* [Digilent Digital Discovery](https://reference.digilentinc.com/test-and-measurement/digital-discovery/start)

* More to come...

## Software

Compatible with Sigrok (via libsigrok), based on the following fork;

* [https://github.com/ultraembedded/libsigrok](https://github.com/ultraembedded/libsigrok)

*open-logic-bit also contains a built in test mode;*

![Demo-counter](docs/pulseview_counter.png)