https://github.com/ultraembedded/riscv_soc
Basic RISC-V Test SoC
https://github.com/ultraembedded/riscv_soc
fpga-soc fpga-soc-linux linux risc-v riscv-linux system-on-chip systemc verilog
Last synced: 28 days ago
JSON representation
Basic RISC-V Test SoC
- Host: GitHub
- URL: https://github.com/ultraembedded/riscv_soc
- Owner: ultraembedded
- Created: 2019-03-16T16:44:58.000Z (about 6 years ago)
- Default Branch: master
- Last Pushed: 2019-04-07T16:54:13.000Z (about 6 years ago)
- Last Synced: 2025-04-07T13:11:15.529Z (about 2 months ago)
- Topics: fpga-soc, fpga-soc-linux, linux, risc-v, riscv-linux, system-on-chip, systemc, verilog
- Language: Verilog
- Size: 6.1 MB
- Stars: 119
- Watchers: 10
- Forks: 31
- Open Issues: 3