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https://github.com/umd-memsys/DRAMSim2

DRAMSim2: A cycle accurate DRAM simulator
https://github.com/umd-memsys/DRAMSim2

c-plus-plus computer-architecture dram simulator

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DRAMSim2: A cycle accurate DRAM simulator

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README 

        
DRAMSim



1. About DRAMSim ---------------------------------------------------------

	DRAMSim is a cycle accurate model of a DRAM memory controller, the DRAM

	modules which comprise system storage, and the bus by which they

	communicate. All major components in a modern memory system are modeled

	as their own respective objects within the source, including: ranks,

	banks, command queue, the memory controller, etc.



	We also added support and config files for STT-MRAM, 

	you can run the simulations the same way as DRAM. 

	Refer Asifuzzaman, K., etc. Enabling a reliable STT-MRAM main memory simulation (MEMSYS2017)

	for more info about STT-MRAM.



	The overarching goal is to have a simulator that is extremely small,

	portable, and accurate. The simulator core has a well-defined interface

	which allows it to be CPU simulator agnostic and should be easily

	modifiably to work with any simulator.  This core has no external run

	time or build time dependencies and has been tested with g++ on Linux

	as well as g++ on Cygwin on Windows.  



2. Building DRAMSim ---------------------------------------------------------



	To build an optimized DRAMSim simply type



	$ make



	For a debug build which contains debugging symbols and verbose output, run:



	$ make DEBUG=1



	this will compile an executable called DRAMSim which can run a

	trace-based simulation. 



	To build the DRAMSim library, type: 



	$ make libdramsim.so 

	



3. Running DRAMSim -----------------------------------------------------------

	

	First, run the preprocessor on the gzipped traces:



	cd traces

	./traceParse.py k6_aoe_02_short.trc.gz



	Then go back to the DRAMSim directory and run the trace based simulator:

	cd ..

	./DRAMSim -t traces/k6_aoe_02_short.trc -s system.ini -d ini/DDR3_micron_64M_8B_x4_sg15.ini -c 10000



4. DRAMSim Output -------------------------------------------------------------



The verbosity of the DRAMSim can be customized in the ini file by turning the

various debug flags on or off in the ini file. 



Below, we have provided a detailed explanation of the simulator output.  With

all DEBUG flags enabled, the following output is displayed for each cycle

executed.  



   NOTE : BP = Bus Packet

	  T  = Transaction

	  MC = MemoryController

	  R# = Rank (index #)



-------------------------------------------------------------

 ----------------- Memory System Update ------------------

 ---------- Memory Controller Update Starting ------------ [8]

 -- R0 Receiving On Bus    : BP [ACT] pa[0x5dec7f0] r[0] b[3] row[1502] col[799]

 -- MC Issuing On Data Bus    : BP [DATA] pa[0x7edc7e0] r[0] b[2] row[2029] col[799] data[0]=

 ++ Adding Read energy to total energy

 -- MC Issuing On Command Bus : BP [READ_P] pa[0x5dec7f8] r[1] b[3] row[1502] col[799]

== New Transaction - Mapping Address [0x5dec800]

  Rank : 0

  Bank : 0

  Row  : 1502

  Col  : 800

 ++ Adding IDD3N to total energy [from rank 0]

 ++ Adding IDD3N to total energy [from rank 1]

== Printing transaction queue

  8]T [Read] [0x45bbfa4]

  9]T [Write] [0x55fbfa0] [5439E]

  10]T [Write] [0x55fbfa8] [1111]

== Printing bank states (According to MC)

[idle] [idle] [2029] [1502] 

[idle] [idle] [1502] [1502] 



== Printing Per Rank, Per Bank Queue

 = Rank 0

    Bank 0   size : 2

       0]BP [ACT] pa[0x5dec800] r[0] b[0] row[1502] col[800]

       1]BP [READ_P] pa[0x5dec800] r[0] b[0] row[1502] col[800]

    Bank 1   size : 2

       0]BP [ACT] pa[0x5dec810] r[0] b[1] row[1502] col[800]

       1]BP [READ_P] pa[0x5dec810] r[0] b[1] row[1502] col[800]

    Bank 2   size : 2

       0]BP [ACT] pa[0x5dec7e0] r[0] b[2] row[1502] col[799]

       1]BP [READ_P] pa[0x5dec7e0] r[0] b[2] row[1502] col[799]

    Bank 3   size : 1

       0]BP [READ_P] pa[0x5dec7f0] r[0] b[3] row[1502] col[799]

 = Rank 1

    Bank 0   size : 2

       0]BP [ACT] pa[0x5dec808] r[1] b[0] row[1502] col[800]

       1]BP [READ_P] pa[0x5dec808] r[1] b[0] row[1502] col[800]

    Bank 1   size : 2

       0]BP [ACT] pa[0x5dec818] r[1] b[1] row[1502] col[800]

       1]BP [READ_P] pa[0x5dec818] r[1] b[1] row[1502] col[800]

    Bank 2   size : 1

       0]BP [READ_P] pa[0x5dec7e8] r[1] b[2] row[1502] col[799]

    Bank 3   size : 0

-----------------------------------------------------



  Anything sent on the bus is encapsulated in an BusPacket (BP) object. 

  When printing, they display the following information:

			 BP [ACT] pa[0x5dec818] r[1] b[1] row[1502] col[800]

  The information displayed  is (in order):command type, physical address,

  rank #, bank#, row #, and column #.



  Lines beginning with " -- " indicate bus traffic, ie, 

     -- R0 Receiving On Bus       : BP [ACT] pa[0x5dec7f0] r[0] b[3] row[1502] col[799]

     -- MC Issuing On Data Bus    : BP [DATA] pa[0x7edc7e0] r[0] b[2] row[2029] col[799] data[0]=

     -- MC Issuing On Command Bus : BP [READ_P] pa[0x5dec7f8] r[1] b[3] row[1502] col[799]

  Sender and receiver are indicated and the packet being sent is detailed.



  Lines beginning with " ++ " indicate power calculations, ie, 

		 ++ Adding Read energy to total energy

 		 ++ Adding IDD3N to total energy [from rank 0]

 		 ++ Adding IDD3N to total energy [from rank 1]

  The state of the system and the actions taken determine which current

  draw is used.  for further detail about each current, see micron data-

  sheet.



	If a pending transaction is in the transaction queue, it will

  be printed, as seen below:

		 == Printing transaction queue		

  	 		1]T [Read] [0x45bbfa4]

  			2]T [Write] [0x55fbfa0] [5439E]

 			  3]T [Write] [0x55fbfa8] [1111]

  Currently, at the start of every cycle, the head of the transaction

  queue is removed, broken up into DRAM commands and placed in the

  appropriate command queues.  To do this, an address mapping scheme

  is applied to the transaction's physical address, the output of 

  which is seen below:

			== New Transaction - Mapping Address [0x5dec800]

  			 Rank : 0

				 Bank : 0

				 Row  : 1502

				 Col  : 800



  If there are pending commands in the command queue, they will be

  printed.  The output is dependent on the designated structure for

  the command queue.  For example, per-rank/per-bank queues are 

  shown below:

   = Rank 1

    Bank 0   size : 2

       0]BP [ACT] pa[0x5dec808] r[1] b[0] row[1502] col[800]

       1]BP [READ_P] pa[0x5dec808] r[1] b[0] row[1502] col[800]

    Bank 1   size : 2

       0]BP [ACT] pa[0x5dec818] r[1] b[1] row[1502] col[800]

       1]BP [READ_P] pa[0x5dec818] r[1] b[1] row[1502] col[800]

    Bank 2   size : 1

       0]BP [READ_P] pa[0x5dec7e8] r[1] b[2] row[1502] col[799]

    Bank 3   size : 0



  The state of each bank in the system is also displayed:

    == Printing bank states (According to MC)

    [idle] [idle] [2029] [1502] 

    [idle] [idle] [1502] [1502] 

  Banks can be in many states, including idle, row active (shown

  with the row that is active), refreshing, or precharging.  These

  states will update based on the commands being sent by the 

  controller.