https://github.com/uttamsdev/risc-cpu-implementation

14-bit CPU implementation in Logisim. This is a 14-bit RISC CPU logisim implementation. All files are included in this single repository.
https://github.com/uttamsdev/risc-cpu-implementation

14bit-cpu risc-cpu-implementation

Last synced: about 1 month ago
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14-bit CPU implementation in Logisim. This is a 14-bit RISC CPU logisim implementation. All files are included in this single repository.

• Host: GitHub
• URL: https://github.com/uttamsdev/risc-cpu-implementation
• Owner: uttamsdev
• Created: 2024-05-30T20:28:53.000Z (12 months ago)
• Default Branch: main
• Last Pushed: 2024-05-30T20:30:28.000Z (12 months ago)
• Last Synced: 2025-03-28T05:31:49.757Z (about 2 months ago)
• Topics: 14bit-cpu, risc-cpu-implementation
• Language: C++
• Homepage:
• Size: 354 KB
• Stars: 4
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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# 14-bit-RISC-CPU-Implementation

14-bit CPU implementation in Logisim. This is a 14-bit RISC CPU logisim implementation. All files are included in this single repository. Datapath, Register Circut,Register File

1 bit ALU, 14 bit ALU, Final ALU, Control Signals and Control Unit

# Designed by Uttam Kumar Saha

# Datapath Design:

![](/Images/datapath.png)

# Register Circuit:

![](Images/regCircuit.png)

# Register File:

![](Images/RegFile.png)

# ALU Circuit:

![](Images/ALU%20circuit.png)

# 1-bit ALU:

![](Images/1-bit-ALU.png)

# 14 bit ALU:

![](Images/14%20bit%20ALU.png)

# Final ALU:

![](Images/final%20ALU.png)

# Shifter Circuit:

![](Images/shifterCircuit.png)

# Control Signals Circuit 1:

![](Images/Control%20Signal%20Circuit1.png)

# Control Signal Circuit 2:

![](Images/Control%20Signal%20Circuit2.png)

# Control Unit 1:

![](Images/control%20unit%201.png)

# Control Unit 2:

![](Images/control%20unit%202.png)