https://github.com/vgalovic/hdl_examples

A collection of VHDL and Verilog examples organized by language and practice section, with setup.tcl files for easy Vivado setup. These examples reflect my FPGA development practice and learning.
https://github.com/vgalovic/hdl_examples

tcl verilog vhdl vivado

Last synced: 6 days ago
JSON representation

A collection of VHDL and Verilog examples organized by language and practice section, with setup.tcl files for easy Vivado setup. These examples reflect my FPGA development practice and learning.

• Host: GitHub
• URL: https://github.com/vgalovic/hdl_examples
• Owner: vgalovic
• License: gpl-3.0
• Created: 2024-12-17T18:09:02.000Z (23 days ago)
• Default Branch: main
• Last Pushed: 2025-01-02T11:02:25.000Z (7 days ago)
• Last Synced: 2025-01-02T12:19:53.803Z (7 days ago)
• Topics: tcl, verilog, vhdl, vivado
• Language: VHDL
• Homepage:
• Size: 69.3 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

        
HDL Examples (VHDL & Verilog)

=============================

This repository contains a collection of HDL (Hardware Description Language) examples that I created while practicing VHDL and Verilog in the *Vivado* environment. The examples are organized into different practice sections to showcase various concepts and techniques in FPGA design.

## Structure

The repository is organized into language-specific folders (`VHDL/` and `Verilog/`), each containing multiple practice sections. Within each practice section, you will find simulation files (`sim/`), source files (`src/`), and a `setup.tcl` script to automate the *Vivado* project setup. This structure is designed to help you easily navigate and work on different sections based on the HDL language you're using.


    HDL_examples/

    ├── <language>/                  - Directory for VHDL/ and Verilog/ examples

    │   └── <practice-section>/      - Directory for a specific practice section

    │      ├── sim/                  - Contains simulation files for the practice section

    │      ├── src/                  - Contains source files for the practice section

    │      └── setup.tcl             - TCL script for seting up the Vivado project for the practice section

    └── create_project.tcl           - TCL script for creating a new Vivado project

    



## Getting Started

To get started with the examples, clone this repository to your local machine:

```bash

git clone https://github.com/vgalovic/HDL_examples.git

```

## Setting Up the Vivado Project

To set up a specific practice section in *Vivado*, use the following command in the TCL console:

```tcl

source /HDL_examples///setup.tcl

```

This will:

- Create a new *Vivado* project in `$HOME/Documents/Vivado`.

- Add all relevant source files and simulation files to the project.

> 📝 **Note:** Make sure to replace ``, ``, and `` with the correct paths based on repository structure.