https://github.com/wardbenjamin/verilogutils

Collection of small utilities to make programming in Verilog easier
https://github.com/wardbenjamin/verilogutils

Last synced: about 2 months ago
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Collection of small utilities to make programming in Verilog easier

• Host: GitHub
• URL: https://github.com/wardbenjamin/verilogutils
• Owner: WardBenjamin
• Created: 2018-11-08T21:42:19.000Z (over 7 years ago)
• Default Branch: master
• Last Pushed: 2018-11-08T21:54:47.000Z (over 7 years ago)
• Last Synced: 2025-01-16T22:43:32.642Z (over 1 year ago)
• Language: Python
• Size: 1.95 KB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
# VerilogUtils

Collection of small utilities to make programming in Verilog easier

## Boolean Algebra Converter

Converts 1/2/3/4-bit boolean algebra from a simple, typable format to valid Verilog code.

Spaces are converted to boolean AND "&" (multiplication), while plus signs are converted to boolean OR "|" (addition).

Inverted inputs are input as a', where a is the non-inverted input.

## Constraint Generator

Generates constraints for given port/pin combinations, in one-line (dictionary) format or in traditional two-property format.

Ex) `set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {CLK}];`

Ex) ```

    set_property PACKAGE_PIN E3 [get_ports {CLK}];

    set_property IOSTANDARD LVCMOS33 [get_ports {CLK}];

    ```

    

Constraints are generated assuming LVCMOS33 I/O Standard (aka 3.3v).