https://github.com/wissance/quickrs232

A versatile full-duplex RS232 FPGA module with interfnal FIFO bufer
https://github.com/wissance/quickrs232

altera-uart fpga fpga-programming fpga-rs232 rs232 serial-communication serial-communication-fpga verilog-library verilog-rs232 verilog-serial-port

Last synced: 18 days ago
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A versatile full-duplex RS232 FPGA module with interfnal FIFO bufer

• Host: GitHub
• URL: https://github.com/wissance/quickrs232
• Owner: Wissance
• License: apache-2.0
• Created: 2023-03-20T18:29:52.000Z (almost 2 years ago)
• Default Branch: master
• Last Pushed: 2024-08-06T19:06:02.000Z (5 months ago)
• Last Synced: 2024-08-06T22:39:10.618Z (5 months ago)
• Topics: altera-uart, fpga, fpga-programming, fpga-rs232, rs232, serial-communication, serial-communication-fpga, verilog-library, verilog-rs232, verilog-serial-port
• Language: Verilog
• Homepage: https://wissance.github.io/QuickRS232/
• Size: 739 KB
• Stars: 1
• Watchers: 3
• Forks: 0
• Open Issues: 7
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
## QuickRS232

![GitHub code size in bytes](https://img.shields.io/github/languages/code-size/wissance/QuickRS232?style=plastic) 

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`QuickRS232` is a versatile `RS232` `FPGA` `Verilog` module with following features:

* ***Internal data buffering*** with `FIFO` builtin in `RS232` with parametric `FIFO` depth;

* ***Full-duplex mode*** (as `RS232` standard supports) with parallel Receive (`Rx`) and Transmit (`Tx`);

* Supports ***either `No Flow Control` mode or Hardware Flow Control*** mode (`RTS + CTS`);

`RS232` timing diagrams (`115200 bod/s`, `even parity`, `no flow control`):

![RS232 Timing diagrams](/img/rs232_full_duplex_mode.png)

`FIFO` timing diagrams

![FIFO Timing diagrams](/img/fifo_diagrams.png)