https://github.com/wissance/quickspi
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
https://github.com/wissance/quickspi
altera axi axi-interfaces bit-oriented-spi dragster-spi fpga hard-spi soft-spi spi spi-fpga spi-hdl spi-interface spi-ip-core spi-pld verilog-components verilog-hdl verilog-snippets verilog-spi xilinx-fpga xilinx-vivado
Last synced: 6 months ago
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Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
- Host: GitHub
- URL: https://github.com/wissance/quickspi
- Owner: Wissance
- License: gpl-3.0
- Created: 2017-04-21T06:47:24.000Z (over 8 years ago)
- Default Branch: master
- Last Pushed: 2017-11-21T19:56:19.000Z (almost 8 years ago)
- Last Synced: 2025-02-09T15:42:51.997Z (8 months ago)
- Topics: altera, axi, axi-interfaces, bit-oriented-spi, dragster-spi, fpga, hard-spi, soft-spi, spi, spi-fpga, spi-hdl, spi-interface, spi-ip-core, spi-pld, verilog-components, verilog-hdl, verilog-snippets, verilog-spi, xilinx-fpga, xilinx-vivado
- Language: Verilog
- Homepage:
- Size: 127 KB
- Stars: 20
- Watchers: 6
- Forks: 7
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- Contributing: CONTRIBUTING.md
- License: LICENSE
- Code of conduct: CODE_OF_CONDUCT.md
Awesome Lists containing this project
README
# QuickSPI
SPI Verilog modules 2 SPI implementations:
1. Fully Hard for FPGA without CPU core like Spartan 6 or Cyclone 4, e.t.c.
features:
- setting bit (MSB, LSB) and bytes order (Little endian or Big endina)
- adjustable number of extra clocks when some devices needs to make internal synchronizzation while CS is still active and clock keep going from clk (Dragster/Awaiba/Cmosis DR-2k-7)
2. Fully soft SPI with AXI Full interface with CPU.
Docs on Russian: https://github.com/OpticalMeasurementsSystems/QuickSPI/wiki/How-to-use-:-%D0%9F%D0%BE%D0%BB%D0%BD%D0%BE%D0%B5-%D1%80%D1%83%D0%BA%D0%BE%D0%B2%D0%BE%D0%B4%D1%81%D1%82%D0%B2%D0%BE