https://github.com/wissance/quickspi

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
https://github.com/wissance/quickspi

altera axi axi-interfaces bit-oriented-spi dragster-spi fpga hard-spi soft-spi spi spi-fpga spi-hdl spi-interface spi-ip-core spi-pld verilog-components verilog-hdl verilog-snippets verilog-spi xilinx-fpga xilinx-vivado

Last synced: 5 days ago
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Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

• Host: GitHub
• URL: https://github.com/wissance/quickspi
• Owner: Wissance
• License: gpl-3.0
• Created: 2017-04-21T06:47:24.000Z (over 7 years ago)
• Default Branch: master
• Last Pushed: 2017-11-21T19:56:19.000Z (about 7 years ago)
• Last Synced: 2023-03-10T02:02:05.270Z (almost 2 years ago)
• Topics: altera, axi, axi-interfaces, bit-oriented-spi, dragster-spi, fpga, hard-spi, soft-spi, spi, spi-fpga, spi-hdl, spi-interface, spi-ip-core, spi-pld, verilog-components, verilog-hdl, verilog-snippets, verilog-spi, xilinx-fpga, xilinx-vivado
• Language: Verilog
• Homepage:
• Size: 127 KB
• Stars: 14
• Watchers: 6
• Forks: 3
• Open Issues: 0

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