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https://github.com/wyvernsemi/mem_model
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
https://github.com/wyvernsemi/mem_model
avalon axi cosimulation dpi-c ghdl memory-model nvc pli questasim simulation test-bench verilator verilog verilog-components verilog-testbenches vhdl vivado-simulator
Last synced: 5 days ago
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High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
- Host: GitHub
- URL: https://github.com/wyvernsemi/mem_model
- Owner: wyvernSemi
- License: gpl-3.0
- Created: 2021-08-02T15:25:23.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2024-11-20T10:42:50.000Z (3 months ago)
- Last Synced: 2024-11-20T12:11:25.037Z (3 months ago)
- Topics: avalon, axi, cosimulation, dpi-c, ghdl, memory-model, nvc, pli, questasim, simulation, test-bench, verilator, verilog, verilog-components, verilog-testbenches, vhdl, vivado-simulator
- Language: VHDL
- Homepage:
- Size: 2.71 MB
- Stars: 22
- Watchers: 3
- Forks: 2
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# High speed C/C++ based behavioural Verilog an VHDL co-simulation memory model
The mem_model component is a Verilog/VHDL simulation test component that allows for a very large memory address space without reserving large amounts of memory, defining large HDL arrays, or building a truncated memory map into a test bench which could be subject to change in the design. The model uses the simulators' programming interfaces to access a C model, pushing the majority of the functionality away from the simulator, making the test bench lightweight, and the memory accesses very fast in simulation compute time.
A direct access API is also provided to allow any other PLI C/C++ code to transfer data directly, without the overhead of simulating bus transactions (see src/mem.h). Wrapper HDL is also provided to map the ports to an AXI subordinate interface (mem_model_axi.v and mem_model_axi.vhd). The default memory mapped slave port and burst ports are Altera Avalon bus compatible.
By default memory is uninitialised but, if compiled with MEM_ZERO_NEW_PAGES defined, memory will be initialised with zeros. By default, the model is big endian, but this can be overridden by defining MEM_MODEL_DEFAULT_ENDIAN=1.
The model's software can be compiled for supporting various HDL languages, with the default being Verilog and using the PLI programming interface. To compile for the VPI interface, MEM_MODEL_PLI_VPI should be defined when compiling the mem_model.c code. When using VHDL then MEM_MODEL_VHDL should be defined. If using the SystemVerilog model then MEM_MODEL_SV should be defined. The model's code, when used with VProc, will also recognise the VProc definitions (VPROC_PLI_VPI, VPROC_VHDL, and VPROC_SV) and if these are defined when compiling the code, then the MEM_MODEL_XXX definitions do not need to be set which are needed only when compiling as a standalone model. If compiling as a stand alone model (i.e. not compiled with VProc) then MEM_MODEL_INTERNAL_PLI must be defined to enable registration of PLI routines when compiling Verilog in Questa and Icarus.
If using Verilog or SystemVerilog models, then the tx_byteenable port is enabled by defining MEM_EN_TX_BYTEENABLE when analysing either mem_model.v or mem_model.sv.
## Summary of HDL files and minimum compile options for each simulator
| Simulator | HDL files | C compilation definitions |
|:-------------------|:-------------------------------|:------------------------------------------|
| *Questa Verilog* | mem_model_q.v | [-DMEM_MODEL_PLI_VPI] [-DMEM_MODEL_INTERNAL_PLI] |
| | mem_model.v | |
| | [mem_model_axi.v] | |
| | | |
| *Icarus Verilog* | mem_model_q.v | [-DICARUS -DMEM_MODEL_INTERNAL_PLI]|
| | mem_model.v | |
| | [mem_model_axi.v] | |
| | | |
| *Verilator* | mem_model_q.v | -DMEM_MODEL_SV |
| | mem_model.sv | |
| | [mem_model_axi.sv] | |
| | | |
| *Vivado xsim* | mem_model_q.v | -DMEM_MODEL_SV |
| | mem_model.sv | |
| | [mem_model_axi.sv] | |
| | | |
| *Questa VHDL* | mem_model_pkg.vhd | -DMEM_MODEL_VHDL |
| | mem_model_q.vhd | |
| | mem_model.vhd | |
| | [mem_model_axi.vhd] | |
| | | |
| *NVC* | mem_model_pkg_nvc.vhd | -DMEM_MODEL_VHDL |
| | mem_model_q.vhd | |
| | mem_model.vhd | |
| | [mem_model_axi.vhd] | |
| | | |
| *GHDL* | mem_model_pkg_ghdl.vhd| -DMEM_MODEL_VHDL |
| | mem_model_q.vhd | |
| | mem_model.vhd | |
| | [mem_model_axi.vhd] | |
More details can be found in the manual—doc/mem_model_manual.pdf.