https://github.com/wyvernsemi/sparc

Sparc version 8 Instruction Set Simulator
https://github.com/wyvernsemi/sparc

32-bits c-plus-plus cpu-model iss processor simulator sparc v8

Last synced: 19 days ago
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Sparc version 8 Instruction Set Simulator

• Host: GitHub
• URL: https://github.com/wyvernsemi/sparc
• Owner: wyvernSemi
• License: gpl-3.0
• Created: 2016-09-25T15:12:02.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2025-02-02T08:30:35.000Z (3 months ago)
• Last Synced: 2025-03-28T09:11:14.269Z (about 1 month ago)
• Topics: 32-bits, c-plus-plus, cpu-model, iss, processor, simulator, sparc, v8
• Language: Assembly
• Homepage: http://www.anita-simulators.org.uk/wyvernsemi
• Size: 1.3 MB
• Stars: 6
• Watchers: 4
• Forks: 3
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
#  Sparc version 8 Instruction Set Simulator







A Sparc v8 Instruction Set Simulator (ISS) written in C, with hooks for external software models and co-simulation. 

The supported instructions are shown below:

```

  Load:          LDSB LDSH LDUB LDUH LD LDD

  Store:         STB STH ST STD

  Atomic:        SWAP LDSTUB

  Misc:          SETHI NOP

  Logical:       AND ANDcc ANDN ANDNcc OR ORcc ORN ORNcc XOR XORcc XNOR XNORcc

  Shift:         SLL SRL SRA

  Add:           ADD ADDcc ADDX ADDXcc 

  Subtract:      SUB SUBcc SUBX SUBXcc

  Multiply:      UMUL UMULcc SMUL SMULcc 

  Divide:        UDIV UDIVcc SDIV SDIVcc

  Tagged add:    TADDcc TADDcc TSUBccTV TSUBccTV

  Multiply Step: MULScc

  Window:        SAVE RESTORE

  Branch:        Bicc

  Prog control:  CALL JMPL 

  Trap:          RETT Ticc

  Read Regs:     RDY RDPSR RDWIM RDTBR 

  Write Regs:    WRY WRPSR WRWIM WRTBR

  Mem Sync:      STBAR FLUSH

  Unimplemented: UNIMP

```

More details of this project can be found in doc/sparc_iss.pdf within this repository.