https://github.com/yasnakateb/chiselprocessor

Multicycle processor in Chisel3
https://github.com/yasnakateb/chiselprocessor

chisel chisel3 computer-architecture cpu mips processor sbt scala

Last synced: 3 days ago
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Multicycle processor in Chisel3

• Host: GitHub
• URL: https://github.com/yasnakateb/chiselprocessor
• Owner: yasnakateb
• Created: 2022-05-17T11:45:44.000Z (over 3 years ago)
• Default Branch: main
• Last Pushed: 2022-05-30T07:21:02.000Z (over 3 years ago)
• Last Synced: 2025-07-03T20:47:47.886Z (3 months ago)
• Topics: chisel, chisel3, computer-architecture, cpu, mips, processor, sbt, scala
• Language: Verilog
• Homepage:
• Size: 145 KB
• Stars: 2
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

          
# ChiselProcessor

### TODO 

 - ✅ Add ALU

 - ✅ Add Control Unit

 - ✅ Add Register File

 - ✅ Add Memory

 - ✅ Add Register

 - ✅ Add Register with enable

 - ✅ Add Control Branch

 - ✅ Add Mux

 - ✅ Add Shifter

 - ✅ Add Sign Extension

 - ⭕ Fix overflow

 - ⭕ Fix PCEn

 - ⭕ Test R_TYPE

 - ⭕ Test LW 

 - ⭕ Test SW

 - ⭕ Test BEQ

 - ⭕ Test ADDI

 - ⭕ Test J 

 - ⭕ Test MFC0 

## Data Path

![](assets/datapath.jpg)