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https://github.com/yugr/gatecheck
Yet another Verilog static analyzer
https://github.com/yugr/gatecheck
clock-g gating static-analysis static-analyzer verilog
Last synced: about 5 hours ago
JSON representation
Yet another Verilog static analyzer
- Host: GitHub
- URL: https://github.com/yugr/gatecheck
- Owner: yugr
- License: mit
- Created: 2019-01-27T07:04:26.000Z (almost 6 years ago)
- Default Branch: master
- Last Pushed: 2019-03-18T12:30:11.000Z (over 5 years ago)
- Last Synced: 2023-03-08T22:25:44.609Z (over 1 year ago)
- Topics: clock-g, gating, static-analysis, static-analyzer, verilog
- Language: Perl
- Size: 9.77 KB
- Stars: 2
- Watchers: 2
- Forks: 0
- Open Issues: 0