https://github.com/yuravg/uvm_tb_cross_bar
SystemVerilog UVM testbench example
https://github.com/yuravg/uvm_tb_cross_bar
systemverilog uvm verification
Last synced: 3 months ago
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SystemVerilog UVM testbench example
- Host: GitHub
- URL: https://github.com/yuravg/uvm_tb_cross_bar
- Owner: yuravg
- License: mit
- Created: 2019-10-18T06:53:34.000Z (over 6 years ago)
- Default Branch: master
- Last Pushed: 2024-05-08T07:47:47.000Z (about 2 years ago)
- Last Synced: 2024-05-08T08:43:06.097Z (about 2 years ago)
- Topics: systemverilog, uvm, verification
- Language: SystemVerilog
- Size: 223 KB
- Stars: 20
- Watchers: 4
- Forks: 10
- Open Issues: 0
-
Metadata Files:
- Readme: README.org
- License: LICENSE
Awesome Lists containing this project
README
#+title: SystemVerilog UVM testbench example
#+author: Yuriy Gritsenko
#+startup: inlineimages
=uvm_tb_cross_bar= is my a SystemVerilog UVM example.
It has DUT, testbench and scripts to run simulation.
* DUT
A =cross_bar= project is used as DUT, this is just a bus switcher([[./rtl/doc/README.md][specification]]).
Used my implementation of this design.
=DUT= implementation is located in the =rtl= directory.
** RTL synthesis
For RTL synthesis is used Intel Quartus Prime, example is located in the =quartus= directory.
#+begin_src text
|-rtl/
#+end_src
* Testbench
The testbench has /bus/ and /cross-bar/ UVC.
/Bus/ UVC has /agent/ and /sequences/.
/Cross-bar/ UVC has /agent/, connecting /layer/ and /sequences/.
The /layer/ provides connectivity /cross-bar/ and /bus/ UVC.
/Env/ has /scoreboard/ and connect /cross-bar/ agents.
The /scoreboard/ is checking results of each /tests/.
/TB/ provides connection /RLT/ to UVM /Test/.
Each /Test/ connects /Env/ to /DUT/ and runs required /virtual_sequences/.
The result of all sequences is checked using /scoreboard/.
#+begin_src text
|-agents/
| |_bus_uvc/
| |_cross_bar_uvc/
-uvm_tb/
|_env/
|_tb/
|_tests/
|_virtual_sequences/
#+end_src
* Simulation
To run simulation of this example used Mentor Graphic's QuestaSim or ModelSim simulator.
Directory =sim= contains files to run simulation.
Following examples of commands to be run from the =sim= directory.
#+begin_src text
|-sim/
#+end_src
** Simulation launch
To run the simulation used console and make-file.
To get list of available commands or =list of tests= should run following command from console:
#+BEGIN_SRC shell-script
$ make help
#+END_SRC
** Run complete verification
Run command from console:
#+BEGIN_SRC shell-script
$ make all_tests
#+END_SRC
The results of each test and a summary of all the tests are displayed in the console.
Each test writes a log and report files: .log, .log.rpt
(report file - it is just reformatted the log file).
*** Log-file output example
[[./images/end_of_test_log.png]]
*** Rpt-file output example
[[./images/end_of_test_rpt.png]]
*** Summary example
[[./images/summary.png]]
** Run some test
At this example there are following ways to run tests:
1. run test in console(without GUI)
2. run test with GUI from console
3. run test from GUI
*** 1. Run test in console(without GUI)
To run test just run command from console:
#+BEGIN_SRC shell-script
$ make
#+END_SRC
- name from =list of tests=
*** 2. run test with GUI from console
Should set empty environment variable /VSIM_MODE/, and run test in console (example for BASH):
#+BEGIN_SRC shell-script
$ export VSIM_MODE=''
$ make
#+END_SRC
or
#+BEGIN_SRC shell-script
$ make VSIM_MODE=''
#+END_SRC
- name from =list of tests=
*** 3. run test from GUI
Run ModelSim/QuestaSim, load aliases, run test.
- Run ModelSim/QuestaSim in =sim= directory
#+BEGIN_SRC shell-script
$ vsim `pwd` &
#+END_SRC
- run in ModelSim/QuestaSim _Transcript_ window
#+BEGIN_SRC tcl
do alias.do
#+END_SRC
- run test
#+BEGIN_SRC tcl
run_
#+END_SRC
* Screenshots
Mentor Graphic's QuestaSim wave
[[./images/wave.png]]
* License
This project is licensed under the MIT License. If not, see [[https://www.opensource.org/licenses/MIT]]